In the need of a Parallel Interface between another component/device, the FlexBus interface is something that would come in hand for us.
But, reading the VF61 Datasheet, at page 32, topic 5.6 about External Memory Bus, is written that:
“Some bus control signals are missing since they are only available on Vybrid pins that are connected to the internal NAND flash (…)”
In other words, the FlexBus is not fully available, is it right?
I would like to hear from you any kind of suggestion or workaround for a data parallel interface using the VF61. If possible, we’d like to use FlexBus.
Thanks.
The FlexBus is not fully available that is right. It is mainly the FB_ALE signal which is missing, which is crucial for a multi-plexed bus. However, in non-multiplexed mode, you should be able to use FlexBus in 8-bit data mode. Please consult the Pinout Designer to get the exact data lines/address lines available.
As an alternative there are DSPI and QuadSPI (a SPI variant which has 4 data lines).
From a software perspective, there is some support for QuadSPI for NOR flash chips since that has been used on the NXP Tower Board. There is no FlexBus support, but it shouldn’t be that complicated. A rough (untested) driver outline would look like this:
Device Tree
flexbus: flexbus@4001e000 {
compatible = "fsl,vf610-flexbus";
reg = <0x4001e000 0x1000>, /* This is the address block of the FlexBus configuration area */
<0x30000000 0xf000000>; /* This is the address block of the FlexBus/parallel Bus */
clock-names = "ipg";
clocks = <&clks VF610_CLK_FLEXBUS>;
status = "okay";
};
Driver
static int __init flexbus_probe(struct platform_device *pdev)
{
struct resource *res;
struct clk *clk;
void __iomem *base;
void __iomem *base_parallel_bus;
int ret;
/* get the resource */
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(base))
return PTR_ERR(base);
/* get the clock */
clk = devm_clk_get(&pdev->dev, NULL);
if (IS_ERR(clk))
return PTR_ERR(clk);
ret = clk_prepare_enable(clk);
if (ret)
return ret;
/*
* Figure out how to set up 8-Bit non-multiplexed FlexBus configuration
* Vybrid Reference Manual, Chapter 10.5 External Bus Interface (FlexBus)
*/
writel(0x0000000, base + 0x8); ...
/* get device memory (second reg) */
res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
base_parallel_bus = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(base))
return PTR_ERR(base);
writel(0xdeadbeef, base_parallel_bus + 0x0);
writel(0xdeadbeef, base_parallel_bus + 0x4);
printk("Read addr 0x0: %8x\n", readl(base_parallel_bus));
printk("Read addr 0x4: %8x\n", readl(base_parallel_bus + 0x4));
return ret;
}
Thanks for your quick answer, Stefan.
We plan on “simulate” the ALE, and with this approach be capable to compensate the multiplexing functionality.
For the Parallel interface, it is needed 24-bit for addressing and 16-bit for data.
Ok, yeah I was about to write that this might be an option, I am not sure if and how well it works. We would be glad to here in case it works for you.
Our hardware engineering team also made this comment which might be helpful:
Theoretically, it could be possible to
use the nCS0 (FB_CS0_b) signal instead
of the ALE. As long as the signal is
high, the content on the bus pins is
interpreted as address. As soon as the
nCS0 signal goes low, the state of the
pins during the previous rising clock
should be latched as addresses. At the
next rising clock edge, the data will
be read by the FPGA or SoC. This is
quite a hack and would probably only
work at low bus speed. At higher
speeds there might be setup and hold
time issues. I also must say that we
have not tried this demultiplexing
solution.
Stefan.tx, thanks again for your support.
For QSPI usage, it would be possible an approach similar to the one used for SPI?
In other words, to create a /dev/qspi0 and access it to transfer data.
I’ve seen the fsl-quadspi.txt in the Kernel Documentation and it give me some light in this topic.
I think that QSPI will be more interesting (or applicable) than FlexBus 
The current QSPI driver is a SPI NOR driver (see drivers/mtd/spi-nor/fsl-quadspi.c). It can talk to serial flash devices and exports them directly as MTD devices. So it does not let you use the bus as /dev/spiX.X would let you do…
That said, the Linux SPI interface has support for multiple data lines (there are flags to indicate the data lines to use, e.g. SPI_RX_QUAD). Also, there are other QSPI drivers in the driver/spi/ subfolder (e.g. spi-ti-qspi.c). But I am not aware of such a driver for the Vybrid QuadSPI IP…
