External Memory Bus Timing Diagrams

I need external bus read/write timing diagrams for T20. I need to interface these modules to an FPGA over the external parallel bus. I did not find this information in the datasheet.

Thank you

Please check Chapter 17.1.1 GMI Functional Waveforms of Tegra 2 Technical Reference Manual

Thank you for the response. Section 17.1.1 shows waveforms for Synchronous and Asynchronous Reads and also Asynchronous Write. However, it does not show waveforms for Synchronous Write. Will appreciate help with this.


We haven’t done any modification to GMI. Related Tegra2 signals routed directly from SOC to module X1 connector. We also don’t have any other information about GMI timing except what was provided by Tegra 2 Reference manual. If you need an additional information please contact NVIDIA.