Enabling RAM ECC on Vybrid

The product sheet for the vf61 (NXP/Freescale Vybrid VF6xx Computer on Module - Arm Cortex A5/M4) states that the 256MB DDR3 RAM can be used in 128MB ECC mode. I’ve tried digging around the Linux source but it’s not immediately obvious to me that this mode is supported. What compile options needs to be set? Do I have to alter the dts? Are there examples of boards that have this enabled by default?


Could you provide the version of the hardware and software of your module? Which carrier board are you using? What is your application?

I am doing preliminary research, the hardware is not set yet. A more specific question I have is how error reporting is handled in Linux, are there ready-made drivers for handling bit error interrupts etc?

The datasheet describes hardware capabilities, unfortunately currently ECC mode is not supported by our Linux BSP.

We made a while ago an effort to try enabling it. In theory, it should be a special sequence during memory initialization in U-Boot. I would assume that if a ECC error during memory access occures, it would lead to some kind of bus abort which then is handled by Linux via a signal/killing the process.

See also:

Well either the ECC correct the error in which case why issue a bus abort, or it doesn’t even detect it in which case why issue a bus abort? Expected behaviour is for controller to correct error, then set some pin high, possibly triggering an interrupt, that’s what I thought at least.

To be clear, I wouldn’t mind a little hacking of my own to get it to work right but before I recommend the product to the customer I would like to know if it is even possible to begin with. Is the reference manual publicly available anywhere?

You can find the Vybrid reference manual online: https://www.nxp.com/docs/en/reference-manual/VFXXXRM.pdf

Quickly glancing at the reference manual in chapter it seems that the behavior is configureable:

00 - ECC not being used. (ECC DRAM is connected, but not being used.)
01 - ECC reporting is on, but automatic correcting feature is disabled.
10 - No ECC RAM storage available. (ECC DRAM is not connected). Use this setting for default case.
11 - ECC reporting and single bit errors will be automatically corrected.

If you want to give it a try yourself, you probably would start building your own U-Boot and try to deploy it. Then you need to tweak memory initialization to make sure it will use ECC. The memory initialization is done in board/toradex/colibri_vf/colibri_vf.c and arch/arm/imx-common/ddrmc-vf610.c. The above NXP community thread and the reference manual should help you to understand what exactly needs to be done…