Hello,
I’m using Toradex Colibri IMX7D 512MB v1.1C with our own pcb and trying to configure UARTA for both cores in same time (Cortex-M4/FreeRTOS and A7/Linux) but without success. Is it possible?
Note: Here we have other product using Colibri VF61. On this product UARTA was configured succefully for both cores.
Note: In our board we have only this UART for debug all system.
Hello @tolentino.jv and Welcome to the Toradex Community!!!
Could you provide the version of the Hardware and Software of your module?
I’m using Toradex Colibri IMX7D 512MB v1.1C with our own pcb and trying to configure UARTA for both cores in same time (Cortex-M4/FreeRTOS and A7/Linux) but without success. Is it possible?
Unfortunately it is not possible to assign the Port to both cores at same times as described here.
Note: Here we have other product using Colibri VF61. On this product UARTA was configured succefully for both cores.
Usually this should not be possible. How did you achieve that?
Note: In our board we have only this UART for debug all system.
If you have any USB Port on your carrier board, then you can use a USB/Converter to Debug Linux and use UARTA for M4.
Best regards,
Jaski
Hello! @jaski.tx
Usually this should not be possible.
How did you achieve that?
On VF61, UARTA is used for debug on linux by default. And on M4 we just configure UARTA like showed in “hello_world” example.
Why this setup works for VF61 and not on iMX7?
If you have any USB Port on your
carrier board, then you can use a
USB/Converter to Debug Linux and use
UARTA for M4.
Our PCB only have UARTA for debugging, other periferals are already in use.
Best regards,
João Tolentino
On VF61, UARTA is used for debug on linux by default. And on M4 we just configure UARTA like showed in “hello_world” example.
Are you sure about that? hello_world is using UART_B as debugging console for M4. Howd did you exactly configure UART_A for M4.
Thanks and best regards,
Jaski
Are you sure about that? hello_world
is using UART_B as debugging console
for M4. Howd did you exactly configure
UART_A for M4.
Yes, the difference between original and our setup is that we change the UART_B for UART_A, but the code is exactly the same.
Thanks,
João
Hi @tolentino.jv
iMX7 features a new Unit called Resource Domain Controller (RDC), which prohibits and grants access to peripherals and memory areas for individual bus masters (e.g. CPU, DMA controller) on hardware level as described here.
You need to correctly set the debug uart to M4 Core and A5 Core Domain by writing this line correctly.
Best regards,
Jaski
Yes, the difference between original
and our setup is that we change the
UART_B for UART_A, but the code is
exactly the same.
Sorry, I made a mistake in that description. In fact, in our code M4 doesn’t read anything from the UART, it only write “Hello World” second after second on UART, and the linux read and write for debug purpose.
Hi @jaski.tx!
I found the definition of the function that you said:
param perm RDC access permission from
RDC domain to peripheral (byte: D3R
D3W D2R D2W D1R D1W D0R D0W)static inline void
RDC_SetPdapAccess(RDC_Type base,
uint32_t pdap, uint8_t perm, bool
sreq, bool lock)
I tried to change the ‘perm’ parameter to 0xFF, and nothing changed.
What is the error? Are you getting kernel crash?
My kernel doesn’t starts when M4 is started.
Colibri iMX7 # boot
Booting from NAND...
ubi0: detaching mtd1
ubi0: mtd1 is detached
ubi0: default fastmap pool size: 200
ubi0: default fastmap WL pool size: 100
ubi0: attaching mtd1
ubi0: scanning is finished
ubi0: attached mtd1 (name "mtd=4", size 508 MiB)
ubi0: PEB size: 131072 bytes (128 KiB), LEB size: 126976 bytes
ubi0: min./max. I/O unit sizes: 2048/2048, sub-page size 2048
ubi0: VID header offset: 2048 (aligned 2048), data offset: 4096
ubi0: good PEBs: 4060, bad PEBs: 4, corrupted PEBs: 0
ubi0: user volume: 4, internal volumes: 1, max. volumes count: 128
ubi0: max/mean erase counter: 40/24, WL threshold: 4096, image sequence number: 2099233846
ubi0: available PEBs: 0, total reserved PEBs: 4060, PEBs reserved for bad PEB handling: 76
No size specified -> Using max size (5564976)
Read 5564976 bytes from volume kernel to 81000000
No size specified -> Using max size (45512)
Read 45512 bytes from volume dtb to 82000000
Kernel image @ 0x81000000 [ 0x000000 - 0x54ea30 ]
## Flattened Device Tree blob at 82000000
Booting using the fdt blob at 0x82000000
Loading Device Tree to 8fff1000, end 8ffff1c7 ... OK
Updating MTD partitions...
Starting kernel ...
Hi @tolentino.jv
I am getting also kernel crash when I am using UARTA on M4 at same time. I think you need to use the RPMSG for multi-core communication as described here.
Best regards,
Jaski
Hi @tolentino.jv
Did you try the solution with Rpmsg? Is the issue solved now?
No. Here we already use rpmsg to communicate between cores in VF61. The idea to use the same uart is for debugging both cores in same time, to test M4, start programming and verify the code.
How can I program rpmsg if i don’t know if my code is working? How can I debug my code?
Dear @tolentino.jv
For debugging the M4 code, you would typically use a JTAG adapter. There’s varous free and paid IDEs supporting this approach.
Regards, Andy
Hi @andy.tx !
As I said before, here we use our own PCB. In future we can do a circuit to use JTAG, but using the actual version of PCB we don’t have this option.
Hi @tolentino.jv
I see two options for you:
Without one of these options, there’s no debug interface, the only thing you can do then is trial-and-error.
Regards, Andy