EIM Peripheral registers updating issue

Technical Support
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1

When we slow down the EIM clock using PRE_PODF bits of CCM_TARGET_ROOT83 register( In our case eim clock source selected is 125 MHz and setting PRE_PODF to divide by 8 ), We observed that sometimes during EIM register initialisation, registers does not get updated by the values we assign to them.

We have used the Map_MemoryWrite() function for peripheral registers and make the mapped variables volatile too. We are using the latest released Toradex CE library.

Please guide us to know the possible reasons of this behaviour.

Regards
Bipin Kumar

2

Dear @bipin7301,

Did you disable the clock before setting the PRE_PODF and then enable the clock? we did like that in our BSP code one such e.g.:

EnableClock(CCGR_GPT1,0);
Target = CLK_ROOT_ON | ENET_AXI_CLK_ROOT_FROM_OSC_24M_CLK |
    CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
    CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
ClockSetTarget(GPT1_CLK_ROOT, Target);
EnableClock(CCGR_GPT1,1);

Sample code for EIM clock setting:

DWORD   *targetAddr = NULL;
imx7Clk->ccmVa = (DWORD *)Map_MapMemory(CCM_BASE_ADDRESS, 0x10000);
targetAddr =  imx7Clk->ccmVa + (CCM_CCGR22 - CCM_BASE_ADDRESS)/4;
*targetAddr &= ~0xFFFFFFFF;
targetAddr = imx7Clk->ccmVa + (CCM_TARGET_ROOT83 - CCM_BASE_ADDRESS)/4;
*targetAddr |= 0x10000000; // Enable clock, OSC_24M selection
targetAddr = imx7Clk->ccmVa + (CCM_CCGR22 - CCM_BASE_ADDRESS)/4;
*targetAddr |= 0x03;       // Set Domain clock needed all the time

Please let us know if it doesn’t help you and could you share you sample code.

Thank you.

3

Dear @raja.tx

We have not disable the clock before setting the PRE_PODF and then enable the clock. However we have followed the steps of EIM clock settings as you have mentioned in sample code.

I am not able to understand the link between clock init and the FTM peripheral register init.
As we first init the clock module for ftm( CCM_CCGR22 and CCM_TARGET_ROOT83), then go for the entire FTM register init and that’s how we did in our project also.

Thanks
Bipin

4

Dear @bipin7301,

Is it Clock disable and change PRE_PODF and enable clock fixing the issue?

Could you share your sample code with us, if it is not fixing the issue?

Could you read 5.2.6.3 Clock Components from the reference manual to more understand about clock gating and shadow register concept?

Please let us know if you have any other queries.

5

Hi Raja,

We were working on Higher frequencies so far and not facing any issue with this interface.
But now as we need to work on lower frequencies again, we are facing the issue again with EIM register settings.

I am describing the issue again as below:
We are developing a smart device application on Visual studio for i.MX7D device using TORADEX SDK and SOM on Colibri i.MX7 EVK board with Win CE 7.

We are using EIM interface for one of our application and found that, When we slow down the EIM clock using( 3.90625 MHz ) PRE_PODF bits of CCM_TARGET_ROOT83 register( In our case eim clock source selected is 125 MHz and setting PRE_PODF to divide by 8 and BCD to Divide by 4), We observed that sometimes during EIM register initialisation, registers does not get updated by the values we assign to them. In fact with these settings CS0RCR1 or CS0WCR1 gets updated with some different settings.

However if we set the EIM clock to higher frequency 15.625 MHz( eim clock source selected is 125 MHz and setting PRE_PODF to divide by 2 and BCD to Divide by 4 ) then there is no issue with register settings and it works as expected.

The behaviour is unpredictable in first case.

Please find below the EIM Initialization code in attachments for your reference and review:link text

We have also tried your suggestion of previous comment “Clock disable and change PRE_PODF and enable clock” but it didn’t made any difference.

Please guide us to resolve the issue.

Thanks in Advance
Bipin

6

Hi Bipin,
Thanks for sharing the code. Let me test it and get back to you.