ECSPI1 chip select not enabled

Technical Support
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1

HI,
I am using Colibri iMX7D with Embedded Linux and FreeRTOS on M4. I am trying to enable the ECSPI1 to use with the freeRTOS in the M4 core. I have disabled the ECSPI1 pins from device tree and configured them in the M4 side. The configurations in M4 side are

// ECSPI1 iomux configuration
/* daisy chain selection */
IOMUXC_ECSPI1_MISO_SELECT_INPUT = 0;
IOMUXC_ECSPI1_MOSI_SELECT_INPUT = 0;


IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK=IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK_MUX_MODE(0);
IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI=IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI_MUX_MODE(0);
IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MISO=IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MISO_MUX_MODE(0);
IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SS0=IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SS0_MUX_MODE(0);


/* pad control */
IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK =    IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_PE_MASK  |
		IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_PS(0)    |      /* pull down */
		IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_DSE(0)   |
		IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_HYS_MASK;

IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI = IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_DSE(0)   |
		IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_HYS_MASK;

IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MISO = IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MISO_HYS_MASK;

IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SS0  =  IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SS0_PE_MASK   |
		IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SS0_PS(3)     |      /* pull up */
		IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SS0_DSE(0)    |
		IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SS0_HYS_MASK;`

I could see that the pins ECSPI1_CLK and ECSPI1_MOSI are configured correctly and the other two pins ECSPI_MISO and ECSPI1_SS0 are not working. Is there anything that I am missing in the configurations?

Regards,
Nishanth

2

Update: I checked with a GPIO in place of Chip-select and in oscilloscope I could see the reply from ADC. This means that the Clock and MOSI are working perfectly, only CS and MISO are not configured correctly. From the iMX7D reference manual, we could see that ALT0 is used for these pins that’s why I put 0 for ECSPI1 pinmuxing. Is it wrong to do so?
Regards,
Nishanth

3

HI @nishanth1829

So you are basically running the code from the example and it is not working for you?

Are you testing this from Linux or U-Boot?

Best regards,
Jaski

4

Hi @jaski.tx , I am using the code from U-Boot only.The example provided is for ECSPI3 but I am trying with ECSPI1. I configured the ECSPI1 in M4 by referring the iMX7D reference manual pg.no 1508 and configurations were given above. I could see that only MOSI and CLK are enabled. In the device tree I just grouped these pins as SPI1 node and disabled that. But while using from U-boot, device tree will not be loaded.So, is the above given configurations for ECSPI1 correct? AM I missing something?
Regards,
Nishanth

5

Hi @nishanth1829

In the device tree I just grouped these pins as SPI1 node and disabled that. But while using from U-boot, device tree will not be loaded.So, is the above given configurations for ECSPI1 correct? AM I missing something?

You need to check if these pins are used in U-Boot or not. U-Boot has his own pin settings.

Best regards,
Jaski

6

Hi @jaski.tx
The pins used under Uboot are defined in /U-boot-toradex/arch/arm/dts/imx7.dtsi , imx7-colibri.dts , imx7d-pinfunc.h files right? I checked in these files but the pins ECSPI1_MISO and ECSPI1_SS0 are not used.

Thanks and regards,
Nishanth

7

Hi @jaski.tx , Is the above given paths correct ?
Regards

8

Hi @nishanth1829

Sorry for the delayed answer.
Yeah, the paths are correct. And it seems these pins are not used in U-Boot.

Could you share the source code of your application, so I can reproduce your issue?

Best regards,
Jaski

9

Hi @jaski.tx ,

I have attached the source Code
ECSPI1_check_code.zip
which is the example ECSPI polling driver provided by Toradex. But I have modified it accordingly to use for ECSPI1. While running this code, Clock and MOSI are working perfectly. When I used a seperate GPIO as Chip Select, I can see the ADC output in Scope. So the MOSI and CLOCK are working. Please do check the pin_mux.c file which has ECSPI1 pin muxing.

Thanks and Regards,
Nishanth

10

Hi @jaski.tx
Did you check with this code? Is the configuration that I did for ECSPI1 right?
Regards,
Nishanth

11

Hi @jaski.tx , In the above(question) mentioned configuration, pins MOSI and CS0 pad registers are wrongly used in place of MUX registers on line number 9 and 10. Also, daisy chain mode where configured wrongly .After changing those correctly, I am able to get the chip select and MISO work perfectly. Regards, Nishanth

12

Thanks for your Input.

What exactly did you change?

13

The daisy chain input for MISO and MOSI were previously set as 0, changing that as 1 as per imx7d ref. manual made the pins to work.The correct configuration for ECSPI1 is

 IOMUXC_ECSPI1_MISO_SELECT_INPUT = 1;
 IOMUXC_ECSPI1_MOSI_SELECT_INPUT = 1;
 IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK=IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK_MUX_MODE(0);
 IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI=IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI_MUX_MODE(0);
 IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MISO=IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MISO_MUX_MODE(0);
 IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SS0=IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SS0_MUX_MODE(0);
 /* pad control */
 IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK =    IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_PE_MASK  |
         IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_PS(0)    |      /* pull down */
         IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_DSE(0)   |
         IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_HYS_MASK;
 IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI = IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_DSE(0)   |
         IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_HYS_MASK;
 IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MISO = IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MISO_HYS_MASK;
 IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SS0  =  IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SS0_PE_MASK   |
         IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SS0_PS(3)     |      /* pull up */
         IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SS0_DSE(0)    |
         IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SS0_HYS_MASK;`

Thanks for you help.
Regards, Nishanth

14

Perfect that it works. Thanks for your Input.