I have a question about the reboot behavior of the Colibri IMX7D module using the internal watchdog.
The imx7d chip is affected by this errata:
e10574: Watchdog: A watchdog timeout or software trigger will not reset the SOC
Description: When the watchdog reset is asserted by software or a timeout, the chip reset sequence is
started but does not complete.
NXP lists multiple workaround options:
Option 1: Hardware implementation of power-on-reset (POR)
Use the pin muxing capability to route the desired WDOG_B signal to an external signal. That
external signal must then be connected at the board level to an active-low power-on control
(PWRON) of the PMIC. When WDOG_B is driven low (by a watchdog timeout or by software),
this will cause the Power Management IC (PMIC) to cycle power causing a system-level
Option 2: Use SRC_A7RCR0[A7_CORE_POR_RESET0] to reset the ARM A7.
This workaround works well for DDR3/DDR3L, but does not work with LPDDR2. LPDDR2
access may fail after the ARM reboots because the LPDDR2 has no dedicated reset pin as
Option 3: Use the SNVS LPCR register to turn off the system power
Set the SNVS_LPCR[TOP] bit through software. Asserting this bit causes a signal to be sent to
the PMIC to turn off the system power. This bit will clear after power is off. This bit is only valid
when the Dumb PMIC mode is enabled (SNVS_LPCR[DP_EN]=1).
This option will work even if the WDOG_B is not connected to the PMIC power-on request
(PWRON). This option will work with either DDR3 or LPDDR2 because the board-level power
Does the toradex BSP implement any of them?
Looking at some imx7d*.dts devicetrees Option 1 seems to be the most common one.
Is there any gpio line connected to the PMIC reset on the Toradex module e.g. MX7D_PAD_GPIO***_WDOG_B?