Hi I need a simple yes/no and how to go about doing it if yes.
From my current research its ambiguous and I need something more definitive.
We’re doing direct MAC to MAC between Verdins, and Ive managed to make it work by putting a physical delay to the RXC and TXC clock signals. (length of wire)
Ive been doing tests with commands like :
fdt set /soc@0/bus@30800000/ethernet@30be0000 tx-internal-delay-ps <2000>
fdt set /soc@0/bus@30800000/ethernet@30be0000 rx-internal-delay-ps <2000>
But it doesnt appear to take any effect. Nor does setting rgmii-id in phy-mode
Does this simply mean the IMX8MP doesnt support hardware level delay or not?
Please let me know.
Thanks
Hi, I’m the Toradex AI Assistant. The Toradex Support team will follow up with you shortly!
Did you like my answer?
Hello!
It seems that the documentation does not provide specific details about hardware-level delay support for the i.MX 8M Plus MAC FEC. While the available resources may not cover the delay commands you mentioned, I can offer some general insights into MAC-to-MAC connections.
In a typical MAC-to-MAC connection, the Media Access Control (MAC) layer is responsible for managing protocol access to the physical network medium. This involves handling frame delimiting, addressing, and error checking. When connecting two MACs directly, it’s important to ensure that both devices are configured to communicate over the same protocol and speed settings to avoid any potential issues.
If you have specific requirements or configurations in mind, feel free to share more details, and I’ll do my best to assist you further.
Best regards,
Toradex AI Assistant.
No, the i.MX8M Plus (i.MX8MP) does not support hardware-level delay adjustments for RGMII TXC/RXC clocks via software. Specifically, it lacks built-in delay line control for RGMII timing adjustments. Therefore, hardware-level delay must be implemented externally, such as through PCB trace length adjustments or physical wire delays, as you’ve done.
1 Like
Thank you for clearing that up for me.
Moving forward I’m going to test a clock buffer ic with about 2ns propagation time. To act as the external delay.
Failing that I will add an extra long trace to the next design. (30cm on top of the normal trace length of the data lines.)
