Customer has managed to make it work so the bus sends the OE with CS0 as read and WE and CS0 as output:
pinctrl_weim_grp: weim-grp {
fsl,pins = <
MX7D_PAD_EPDC_DATA09__EIM_RW 0x14 /* SODIMM 89 */
MX7D_PAD_EPDC_DATA08__EIM_OE 0x14 /* SODIMM 91 */
MX7D_PAD_EPDC_DATA10__EIM_CS0_B 0x14 /* SODIMM 105 */
MX7D_PAD_EPDC_DATA12__EIM_LBA_B 0x14 /* SODIMM 150 */
MX7D_PAD_EPDC_DATA00__EIM_AD0 0x14 /* SODIMM 111 */
MX7D_PAD_EPDC_DATA01__EIM_AD1 0x14 /* SODIMM 113 */
MX7D_PAD_EPDC_DATA02__EIM_AD2 0x14 /* SODIMM 115 */
MX7D_PAD_EPDC_DATA03__EIM_AD3 0x14 /* SODIMM 117 */
MX7D_PAD_EPDC_DATA04__EIM_AD4 0x14 /* SODIMM 119 */
MX7D_PAD_EPDC_DATA05__EIM_AD5 0x14 /* SODIMM 121 */
MX7D_PAD_EPDC_DATA06__EIM_AD6 0x14 /* SODIMM 123 */
MX7D_PAD_EPDC_DATA07__EIM_AD7 0x14 /* SODIMM 125 */
MX7D_PAD_EPDC_BDR1__EIM_AD8 0x14 /* SODIMM 110 */
MX7D_PAD_EPDC_PWR_COM__EIM_AD9 0x14 /* SODIMM 112 */
MX7D_PAD_EPDC_SDOE__EIM_AD12 0x14 /* SODIMM 118 */
MX7D_PAD_EPDC_SDSHR__EIM_AD13 0x14 /* SODIMM 120 */
MX7D_PAD_EPDC_GDCLK__EIM_ADDR18 0x14 /* SODIMM 132 */
MX7D_PAD_EPDC_GDOE__EIM_ADDR19 0x14 /* SODIMM 134 */
MX7D_PAD_EPDC_GDSP__EIM_ADDR21 0x14 /* SODIMM 104 */
};
&weim {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_weim_grp>;
#address-cells = <2>;
#size-cells = <1>;
/* <cs-number> 0 <physical address of mapping> <size> */
ranges = <0 0 0x28000000 0x02000000>, /* 32MB CS0 */
<1 0 0x2A000000 0x02000000>, /* 32MB CS1 */
<2 0 0x2C000000 0x02000000>, /* 32MB CS2 */
<3 0 0x2E000000 0x02000000>; /* 32MB CS3 */
status = "okay";
fsl,weim-cs-gpr = <&gpr>;
assigned-clock-rates = <66000000>;
imx-weim@0,0 {
compatible = "fsl,imx6q-weim";
reg = <0 0 0x02000000>;
#address-cells = <1>;
#size-cells = <1>;
bank-width = <2>;
/* CSxGCR1, CSxGCR2, CSxRCR1, CSxRCR2, CSxWCR1, CSxWCR2. */
/* Valores de Reset 0x00010080 0x00001000 0x00000000 0x00000000 0x00000000 0x00000000 */
fsl,weim-cs-timing = <0x00e40089 0x00001130 0x3f291111 0x00000000 0xff249249 0x00000000>;
};
imx-weim@1,0 {
compatible = "fsl,imx6q-weim";
reg = <1 0 0x02000000>;
#address-cells = <1>;
#size-cells = <1>;
bank-width = <2>;
/* CSxGCR1, CSxGCR2, CSxRCR1, CSxRCR2, CSxWCR1, CSxWCR2. */
fsl,weim-cs-timing = <0x00e10089 0x00001130 0x02010000 0x00000000 0x06040600 0x00000000>;
};