Configuring SPI1 on Colibri iMX7 Using Two Chip Select (CS) Pins via Device Tree Overlay

Technical Support
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1

Hi everyone,

I’m working with a Colibri iMX7 module (eMMC version) with Aster Carrier Board and attempting to configure SPI1 with two Chip Select (CS) pins using a custom device tree overlay. Specifically, I want to use the following configuration:
SPI1 Interface
CS0 assigned to SODIMM Pin 86
CS1 assigned to SODIMM Pin 79

I’ve created a device tree overlay file (imx7d-colibri-spi1-overlay.dts) to configure these CS pins, but I’m not entirely sure if the assignments and configuration are correct. Below is a simplified version of my device tree overlay:

/dts-v1/;
/plugin/;

/ {
    compatible = "toradex,colibri-imx7";

    fragment@0 {
        target = <&ecspi1>;
        __overlay__ {
            status = "okay";

            /* Define the CS pins */
            cs-gpios = <
                &gpio3 6 GPIO_ACTIVE_LOW  /* CS0: GPIO3_IO06 (SODIMM 86) */
                &gpio2 23 GPIO_ACTIVE_LOW /* CS1: GPIO2_IO23 (SODIMM 79) */
            >;

            num-cs = <2>;
        };
    };

    /* Pin configuration for CS0 (SODIMM 86, GPIO3_IO06) */
    fragment@1 {
        target = <&iomuxc>;
        __overlay__ {
            pinctrl_ecspi1_cs0: ecspi1cs0grp {
                fsl,pins = <
                    MX7D_PAD_SAI2_RX_SYNC__GPIO3_IO06 0x14 /* Correct for SODIMM 86 */
                >;
            };
        };
    };

    /* Pin configuration for CS1 (SODIMM 130, GPIO2_IO23) */
    fragment@2 {
        target = <&iomuxc>;
        __overlay__ {
            pinctrl_ecspi1_cs1: ecspi1cs1grp {
                fsl,pins = <
                    MX7D_PAD_ENET2_RGMII_TX_CTL__GPIO2_IO23 0x14 /* Correct for SODIMM 130 */
                >;
            };
        };
    };

    /* Attach the pin configurations to ecspi1 */
    fragment@3 {
        target = <&ecspi1>;
        __overlay__ {
            pinctrl-names = "default";
            pinctrl-0 = <&pinctrl_ecspi1_cs0 &pinctrl_ecspi1_cs1>;
        };
    };
};

My Questions:

  1. Does the above device tree overlay look correct for configuring SPI1 with CS0 on GPIO3_IO06 (SODIMM 86) and CS1 on GPIO2_IO23 (SODIMM 79)?
  2. Are there any specific considerations I should be aware of when configuring these GPIO pins for SPI on the Colibri iMX7?
  3. After applying the overlay and rebooting, what would be the best way to verify if the configuration is correct?
  4. If there are better practices for assigning multiple CS pins on SPI in this setup, I’d love to hear your suggestions!

Any advice, corrections, or pointers would be greatly appreciated!

Thanks in advance!

2

Hi @trainyinfi!

On our Colibri iMX7 device tree, we already have a node for SPI, you can find it on linux kernel git, line 148. Besides, we have a device tree overlay to enable spidev, it is called colibri-imx7_spidev_overlay.dts.

I recommend using our overlay as a starting point and adding your changes. Please, be aware that the GPIO pin must be available, it means it cannot be called/reserved for any other function. In case it is reserved for another function, you can disable the node or use another GPIO.

In your case, the SODIMM 86 is already defined as a CS for SPI, and the SODIMM 79 as a GPIO (so you can use it).
If you are not familiar with device trees or device tree overlays, I recommend reading the following articles:

In order to verify the configuration, you can follow this article.

Feel free to ask if you have any doubts or issues.
Lucas Azeituno