Colibri vf50 to imx6ull ethernet device tree port

Technical Support
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1

I am a software guy trying to swap out a VF50 colibri module, replacing it with an imx6ull colibri module on a custom carrier. The original custom board design was based on the iris board.
I have the boot loader, kernel, rootfs and my app running.
All I lack is getting the ethernet ports to work on the custom carrier. I am pretty sure that I need to change the device tree, but I am struggling to understand how to translate the original VF50 device tree changes to the imx6ull.
It looks like the custom board is taking a reference clock from SODIMM pin 89 and setting the clock rate to 50MHZ.

Here is what I think is the relevant change in the VF50 device tree form the original iris carrier board:
in the file: vf-colibri.dtsi

original:
&clks {
assigned-clocks = <&clks VF610_CLK_ENET_SEL>,
<&clks VF610_CLK_ENET_TS_SEL>;
assigned-clock-parents = <&clks VF610_CLK_ENET_50M>,
<&clks VF610_CLK_ENET_50M>;
};

changed to:
&clks {
assigned-clocks = <&clks VF610_CLK_ENET_SEL>,
<&clks VF610_CLK_ENET_TS_SEL>;
assigned-clock-parents = <&clks VF610_CLK_ENET_EXT>,
<&clks VF610_CLK_ENET_EXT>;
assigned-clock-rates = <50000000>, <50000000>;
};

original:

pinctrl_fec1: fec1grp {
fsl,pins = <
VF610_PAD_PTA6__RMII_CLKOUT 0x30d2
VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2
VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3
VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1
VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1
VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1
VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1
VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2
VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2
VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2
>;
};

changed to:
pinctrl_fec1: fec1grp {
fsl,pins = <
/VF610_PAD_PTA6__RMII_CLKOUT 0x30d2/
VF610_PAD_PTA9__RMII_DELAY_CLKIN 0x30d1
VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2
VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3
VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1
VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1
VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1
VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1
VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2
VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2
VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2
>;
};

Can you point me in the right direction in translating this hardware description into the imx6ull?
My current device tree is a copy of the imx6ull-colibri-iris-v2.dts.
Thank you.

Software summary

Bootloader: U-Boot
Kernel version: 6.1.55-6.0.0-00018-g61ddaacaf55a #1 SMP Fri May 10 18:03:57 MDT 2024
Kernel command line: user_debug=30 ubi.mtd=ubi root=ubi0:rootfs rw rootfstype=ubifs ubi.fm_autoconvert=1 console=tty1 console=ttymxc0,115200n8 consoleblank=0 video=mxsfb:640x480M-16@60
Distro name: NAME=“TDX Wayland with XWayland Upstream”
Distro version: VERSION_ID=6.5.0-build.9
Distro variant: -
Hostname: -

Hardware info

HW model: Toradex Colibri iMX6ULL 256M/512B on Colibri Encelium Wireless Manager
Toradex version: 0045 V1.1A
Serial number: 06847182
Processor arch: armv7l

root@localhost:~# tdx-info -dt

Device tree

Device tree enabled: -
Compatible string: toradex,colibri-imx6ull-wm-v2toradex,colibri-imx6ullfsl,imx6ull
Device trees available: -

Device tree overlays

Overlays enabled: -
Overlays available: -

2

Hi, I’m the Toradex AI Assistant. I’m in early beta, and I would appreciate your feedback.
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:+1: :-1:

:handshake:

To translate the Ethernet configuration from the VF50 to the i.MX6ULL, you’ll need to adjust the device tree for the i.MX6ULL to match the clock and pin configurations of your custom carrier board. Here are the steps to help you with this process:

  1. Clock Configuration:
    The VF50 uses VF610_CLK_ENET_EXT for the external clock, while the i.MX6ULL will use a different clock source. You need to find the equivalent clock source for the i.MX6ULL and set it to 50MHz.

    In your imx6ull-colibri-iris-v2.dts, you should modify the clock settings. Typically, the i.MX6ULL uses clks node for clock configurations. Here is an example of how you might set it:

    &clks {
    assigned-clocks = <&clks IMX6ULL_CLK_ENET_SEL>,
                      <&clks IMX6ULL_CLK_ENET_TS_SEL>;
    assigned-clock-parents = <&clks IMX6ULL_CLK_ENET_EXT>,
                             <&clks IMX6ULL_CLK_ENET_EXT>;
    assigned-clock-rates = <50000000>, <50000000>;
};

    Ensure you replace IMX6ULL_CLK_ENET_EXT with the correct clock source for the i.MX6ULL.

  2. Pin Configuration:
    The pin configuration for the Ethernet interface will also need to be updated. The i.MX6ULL uses different pin names and configurations compared to the VF50. You need to map the VF50 pin configurations to the corresponding i.MX6ULL pins.

    Here is an example of how you might configure the pins in the imx6ull-colibri-iris-v2.dts:

    &pinctrl_fec1 {
    fsl,pins = <
        MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK 0x1b0b1
        MX6UL_PAD_ENET1_MDC__ENET1_MDC 0x1b0b1
        MX6UL_PAD_ENET1_MDIO__ENET1_MDIO 0x1b0b1
        MX6UL_PAD_ENET1_CRS__ENET1_CRS 0x1b0b1
        MX6UL_PAD_EN
3

I am having trouble finding anything like: IMX6ULL_CLK_ENET_SEL.

I noticed that on the imx6ull, there are clocks being specified in the fec2: block:
fec2: ethernet@20b4000 {
compatible = “fsl,imx6ul-fec”, “fsl,imx6q-fec”;
reg = <0x020b4000 0x4000>;
interrupt-names = “int0”, “pps”;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6UL_CLK_ENET>,
<&clks IMX6UL_CLK_ENET_AHB>,
<&clks IMX6UL_CLK_ENET_PTP>,
<&clks IMX6UL_CLK_ENET2_REF_125M>,
<&clks IMX6UL_CLK_ENET2_REF_125M>;
clock-names = “ipg”, “ahb”, “ptp”,
“enet_clk_ref”, “enet_out”;
fsl,num-tx-queues = <1>;
fsl,num-rx-queues = <1>;
fsl,stop-mode = <&gpr 0x10 4>;
fsl,magic-packet;
status = “disabled”;
};
Does anything need to change there, or can you point me to the equivalent of IMX6ULL_CLK_ENET_SEL and IMX6ULL_CLK_ENET_TS_SEL

4

Could you please provide a snippet of your custom carrier board schematics related to the Ethernet port that isn’t working?

5

This is some work that we did to try and understand how the ethernet is wired on the our custom carrier board.

image
image2656×1528 274 KB

The schematic is actually for the second ethernet port which is configured in a similar way on the VF50. The existing device tree node is:

	pinctrl_fec0: fec0grp {
		fsl,pins = <
			VF610_PAD_PTA9__RMII_DELAY_CLKIN	0x30d1
			VF610_PAD_PTC0__ENET_RMII0_MDC		0x30d2
			VF610_PAD_PTC1__ENET_RMII0_MDIO		0x30d3
			VF610_PAD_PTC2__ENET_RMII0_CRS		0x30d1
			VF610_PAD_PTC3__ENET_RMII0_RXD1		0x30d1
			VF610_PAD_PTC4__ENET_RMII0_RXD0		0x30d1
			VF610_PAD_PTC5__ENET_RMII0_RXER		0x30d1
			VF610_PAD_PTC6__ENET_RMII0_TXD1		0x30d2
			VF610_PAD_PTC7__ENET_RMII0_TXD0		0x30d2
			VF610_PAD_PTC8__ENET_RMII0_TXEN		0x30d2
                           /* Disable pads multiplexed with PTC7/PTC6 
                            VF610_PAD_PTB0__GPIO_22                 0x0000
                            VF610_PAD_PTB9__GPIO_31                 0x0000*/
		>;
	};
6

The RMII signals on the Colibri iMX6ULL and Colibri VF50 modules are not compatible, as they are located on different pins of the X1 connector. This issue cannot be resolved through Device Tree modifications; a redesign of the carrier board is required.

7

@mike.whatcott,

It is not clear from your DT excepts, were you using 2-ports L2 switch on VF (quite unique VF feature) or just two standalone ethernet ports? If indeed you need 2-ports Ethernet switch feature, then you need some external device for it to use with iMX6ULL.

8

Thank you.

9

One more related question: Should I be able to swap in vf61 colibri board for the vf50 and be able to use the existing network setup?

10

Yes, you can swap in the Colibri VF61 module, and you can keep the DT Ethernet-related nodes from the VF50 as is