Colibri VF50 dual ehernet problem

We are building a carrier board for colibri VF50 / VF61 module.
We want to connect the external RMII interface with a switch (Davicom DM8603) instead of a “normal” PHY.
I have modified my device tree files to activate the second ethernet controller and the RMII interface as in the example from vf-colibri-dual-eth.dtsi:

				VF610_PAD_PTA9__RMII_CLKOUT		0x30d2
				VF610_PAD_PTC0__ENET_RMII0_MDC		0x30d2
				VF610_PAD_PTC1__ENET_RMII0_MDIO		0x30d3
				VF610_PAD_PTC2__ENET_RMII0_CRS		0x30d1
				VF610_PAD_PTC3__ENET_RMII0_RXD1		0x30d1
				VF610_PAD_PTC4__ENET_RMII0_RXD0		0x30d1
				VF610_PAD_PTC5__ENET_RMII0_RXER		0x30d1
				VF610_PAD_PTC6__ENET_RMII0_TXD1		0x30d2
				VF610_PAD_PTC7__ENET_RMII0_TXD0		0x30d2
				VF610_PAD_PTC8__ENET_RMII0_TXEN		0x30d2
				/* Disable pads multiplexed with PTC7/PTC6 */
				VF610_PAD_PTB0__GPIO_22			0x0000
				VF610_PAD_PTB9__GPIO_31			0x0000

During the boot, I see the 2 fec devices, but the external one see only a “Generic PHY”

[   32.134814] fec 400d0000.ethernet eth0: Freescale FEC PHY driver [Generic PHY] (mii_bus:phy_addr=400d0000.eth)
[   32.163094] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
[   32.270817] fec 400d1000.ethernet eth1: Freescale FEC PHY driver [Micrel KSZ8041] (mii_bus:phy_addr=400d1000.)
[   32.302695] IPv6: ADDRCONF(NETDEV_UP): eth1: link is not ready

# mii-tool -vv eth1
Using SIOCGMIIPHY=0x8947
eth1: negotiated 100baseTx-FD, link ok
  registers for MII PHY 1: 
    3000 786d 0022 1513 01e1 c5e1 000f 0000
    0000 0000 0000 0000 0000 0000 0000 0000
    0000 0000 0000 0000 0001 0000 0600 0000
    0000 0000 0000 0029 0018 0000 0000 0000
  product info: Micrel KSZ8041 rev 3
  basic mode:   autonegotiation enabled
  basic status: autonegotiation complete, link ok
  capabilities: 100baseTx-FD 100baseTx-HD 10baseT-FD 10baseT-HD
  advertising:  100baseTx-FD 100baseTx-HD 10baseT-FD 10baseT-HD
  link partner: 100baseTx-FD 100baseTx-HD 10baseT-FD 10baseT-HD flow-control
# mii-tool -vv eth0
Using SIOCGMIIPHY=0x8947
eth0: 10 Mbit, half duplex, no link
  registers for MII PHY 0: 
    0000 f800 0000 f000 0000 f800 0000 0000
    0000 f800 0000 0000 0000 0000 0000 f000
    0000 0000 0000 fc00 0000 f000 0000 f000
    0000 f800 0000 fc00 0000 0000 0000 0000
  product info: vendor 00:00:3c, model 0 rev 0
  basic mode:   10 Mbit, half duplex
  basic status: no link
  capabilities: 100baseT4 100baseTx-FD 100baseTx-HD 10baseT-FD 10baseT-HD

In the reality, the PHY management interface is not working as expected.
With a logic analyser, I see a usefull signal on the MDIO pin, but no clock on the MDC pin.
Instead of a clock, I have a voltage of about 1.8 V (looks not like a digital output).
I have more or less the same voltage on the colibri side if I disconnect the connection to the PHY.
The MDC pin of my PHY is connected to the Colibri SODIMM pin 71 (checked).

Is there any “tricks” with this MDC pin, or what else could be wrong ?

With kind regards.

Is your secondary PHY connected according to the reference schematics available here?

It seems as if the MDC pin did not get properly muxed. Can you check (post) the complete output of dmesg? Also /sys/kernel/debug/pinctrl/pinctrl-handles is helpful to see whether pinmux got properly applied.