Colibri VF50/61 UART 3 and 4 not working after custom DTB

Hello,

currently we are trying to make some serial transactions with UART 3 and 4. We are using both Colibri VF50 and VF61 for tests with the same outcome. BSP is Colibri_VF_LinuxImageV2.5 with a custom DTB.

We’ve followed your Vybrid based device tree customization tutorial (http://developer.toradex.com/device-tree-customization#Vybrid_based_Modules) in order to create another DTB with UART3 and 4 with status = okay (I shall leave the dts and dtb attached).

Just for a quick test, only DTBs are updated, kernel is left untouched. NAND flashed from SD and /dev/ttyLP3 and /dev/ttyLP4 correctly appear after booting (TFT doesn’t work and before login I’m having a info message of task blocked repeating itself every 10 seconds - these are not the issue, for now).

Checking Colibri Datasheet, the only reference that I find regarding UART3 and 4 pinout are SODIMM 29/31 for UART3_RX, SODIMM 23/37 for UART3_TX, SODIMM 53 for UART4_RX amd SODIMM 51 for UART4_TX. After getting the ports stty’d , I’m trying to get some data transmitted (echo “foobar” > /dev/ttyLP2) or recieved (cat /dev/ttyLP2) through these pins, but no data is received nor transmitted.

My guess is that maybe I’m missing some pinmux set for those UART but I couldn’t find any more info saying that in the tutorials, although checking vf-colibri.dtsi I find some interesting fields that seem to set the uart0, uart1 and uart2 pins through pinctrl_uart0, pinctrl_uart1 and pinctrl_uart2, respectively.

Thanks,
Álvaro.

currently we are trying to make some serial transactions with UART 3 and 4. We are using both Colibri VF50 and VF61 for tests with the same outcome. BSP is Colibri_VF_LinuxImageV2.5 with a custom DTB.

We’ve followed your Vybrid based device tree customization tutorial (http://developer.toradex.com/device-tree-customization#Vybrid_based_Modules) in order to create another DTB with UART3 and 4 with status = okay (I shall leave the dts and dtb attached).

Can you provide the exact changes done in device tree/s, to enable the additional UART’s ? Output of git diff should be helpful.

Just for a quick test, only DTBs are updated, kernel is left untouched. NAND flashed from SD and /dev/ttyLP3 and /dev/ttyLP4 correctly appear after booting (TFT doesn’t work and before login I’m having a info message of task blocked repeating itself every 10 seconds - these are not the issue, for now).

Not sure about which kernel version you are trying to cross-compile, please make sure you update both Linux kernel and device tree blobs to avoid confusions/problems.

Checking Colibri Datasheet, the only reference that I find regarding UART3 and 4 pinout are SODIMM 29/31 for UART3_RX, SODIMM 23/37 for UART3_TX, SODIMM 53 for UART4_RX amd SODIMM 51 for UART4_TX. After getting the ports stty’d , I’m trying to get some data transmitted (echo “foobar” > /dev/ttyLP2) or recieved (cat /dev/ttyLP2) through these pins, but no data is received nor transmitted.

At least ttyLP2 should work out-of-the-box, you are checking on UART_B pins right ?
Refer this article for information related to mapping of ttyLPX → UART_X.

My guess is that maybe I’m missing some pinmux set for those UART but I couldn’t find any more info saying that in the tutorials, although checking vf-colibri.dtsi I find some interesting fields that seem to set the uart0, uart1 and uart2 pins through pinctrl_uart0, pinctrl_uart1 and pinctrl_uart2, respectively.

As an example, have a look at this device tree which has pin-mux configurations for UART3 and UART4.

Can you provide the exact changes done in device tree/s, to enable the additional UART’s ? Output of git diff should be helpful.

Here you go:

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index dd806e1..ee6b086 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -357,6 +357,7 @@ dtb-$(CONFIG_SOC_LS1021A) += \
 dtb-$(CONFIG_SOC_VF610) += \
 	vf500-colibri-eval-v3.dtb \
 	vf610-colibri-eval-v3.dtb \
+	vf610-colibri-my-carrier.dtb \
 	vf610m4-colibri.dtb \
 	vf500-colibri-dual-eth.dtb \
 	vf610-colibri-dual-eth.dtb \

vf610-colibri-my-carrier both dts and dtb can be found attached in the original post.

At least ttyLP2 should work out-of-the-box, you are checking on UART_B pins right ? Refer this article for information related to mapping of ttyLPX → UART_X.

Yeah sorry, ttyLP0, ttyLP2 and ttyLP1 all work out-of-the-box, the problem is when trying to apply this to ttyLP3 and ttyLP4.

Not sure about which kernel version you are trying to cross-compile, please make sure you update both Linux kernel and device tree blobs to avoid confusions/problems.

Kernel from linux-toradex is 4.4.39 according to KConfig, while the one that works is the default Kernel 4.1.15-v2.5b3+ge6d111c. I’ve already tried compiling and updating zImage, which leaves me stuck at “Starting Kernel”.

As an example, have a look at this device tree which has pin-mux configurations for UART3 and UART4.

Thanks, this worked! In which part of the documentation are those 0x21a2, 0x21a1 defined? I’m not sure what do they mean or how can I use them in the future.

Thanks again,
Álvaro.

Thanks, this worked! In which part of the documentation are those 0x21a2, 0x21a1 defined? I’m not sure what do they mean or how can I use them in the future.

Information related to pin-mux configurations is documented in this article