Colibri iMX8X: MCLK for Audio Codec (CS4270-CZZ)

Hi team,

A customer is migrating from another system where they are using a CS4270-CZZ as Audio Codec to reproduce some samples where a MCLK signal of 12.288MHz is used.

The customer is asking how they can do this with Colibri iMX8X. They thought about using one of the other clocks for this since they are also using the LCD so the current MCLK is not available.

It seems they are using the “Slave Mode - Single Speed” of the CS4270-CZZ so the Audio Codec MCLK needs to be in sync with the source, so it has to come from the module (No external oscillator),.

However, not the customer nor myself exactly know if any other clock specification can be used: They just used a 12.288MHz clock until now, and we don’t have more details on why is this. This is the info we have need:


So 2 questions:

  1. Can we use some other frequency rather than 12.288MHz?
  2. What clocks can we use? (If 1 is no, what clocks can generate this 12.288MHz).

Thanks and kind regards,

Looking at our some of our device trees, we can see that the 12288Mhz clock is listed as an option to be used for our codecs:

        sgtl5000: codec@a {                                                                                                                                                                                                                                                                                                     
                compatible = "fsl,sgtl5000";                                                                                                                                                                                                                                                                                    
                pinctrl-names = "default";                                                                                                                                                                                                                                                                                      
                pinctrl-0 = <&pinctrl_sgtl5000>;                                                                                                                                                                                                                                                                                
                #sound-dai-cells = <0>;                                                                                                                                                                                                                                                                                         
                assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,                                                                                                                                                                                                                                                
                                <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,                                                                                                                                                                                                                                              
                                <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,                                                                                                                                                                                                                                              
                                <&mclkout0_lpcg 0>;                                                                                                                                                                                                                                                                             
                assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>;                                                                                                                                                                                                                                         
                clocks = <&mclkout0_lpcg 0>;                                                                                                                                                                                                                                                                                    
                clock-names = "mclk";                                                                                                                                                                                                                                                                                           
                reg = <0x0a>;                                                                                                                                                                                                                                                                                                   
                VDDA-supply = <&reg_module_3v3_avdd>;                                                                                                                                                                                                                                                                           
                VDDD-supply = <&reg_vref_1v8>;                                                                                                                                                                                                                                                                                  
                VDDIO-supply = <&reg_module_3v3>;                                                                                                                                                                                                                                                                               

Because of this I would say that if the customer wants to keep using the same clock, it should be possible. Other possible clocks are listed there as well.
If the codec is not configured in standalone mode (i.e. it has the I2C lines connected), it can be controlled by software. Here’s the clock initialization function from the codec driver in the linux kernel:

 * cs4270_set_dai_sysclk - determine the CS4270 samples rates.                                                                                                 
 * @codec_dai: the codec DAI                                                                                                                                   
 * @clk_id: the clock ID (ignored)                                                                                                                             
 * @freq: the MCLK input frequency                                                                                                                             
 * @dir: the clock direction (ignored)                                                                                                                         
 * This function is used to tell the codec driver what the input MCLK                                                                                          
 * frequency is.                                                                                                                                               
 * The value of MCLK is used to determine which sample rates are supported                                                                                     
 * by the CS4270.  The ratio of MCLK / Fs must be equal to one of nine                                                                                         
 * supported values - 64, 96, 128, 192, 256, 384, 512, 768, and 1024.                                                                                          
 * This function calculates the nine ratios and determines which ones match                                                                                    
 * a standard sample rate.  If there's a match, then it is added to the list                                                                                   
 * of supported sample rates.                                                                                                                                  

This gives a good idea of what clock rates should be supported by the codec, and it reflects the table given in the question.

Best regards,
Rafael Beims