Colibri IMX8QX(2 GB RAM) -> Extend Ram size for cortex M4

Hi,
I am using Colibri IMX8Qx 2GB SOC module and we need to expand M4 code memory to 2 MB.
I have following queries can you please help us,

  1. Partition of DDR RAM between M4 core and Linux is done .?
    2)Address range of Linux and M4 core in DDR RAM.?
    3)How we can extend the cortex M4 RAM.?

Regards,
Ouseppachan CR

Hi, I’m the Toradex AI Assistant. I’m in early beta, and I would appreciate your feedback.
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Hello,

To address your queries regarding the Colibri iMX8Qx 2GB SoC module and the expansion of the Cortex-M4 code memory:

  1. Partition of DDR RAM between M4 core and Linux: Yes, the partitioning of DDR RAM between the M4 core and Linux is possible and is typically done through the U-Boot environment or via the Device Tree. This configuration defines specific memory regions that are reserved for the M4 core, ensuring that Linux does not use these regions, thus preventing conflicts.

  2. Address range of Linux and M4 core in DDR RAM: The specific address range allocated to Linux and the M4 core can vary based on your system’s configuration. This is defined in the Device Tree or U-Boot environment settings. Typically, you would reserve a portion of the DDR RAM for the M4 core by specifying the memory region’s start address and size. The exact values depend on your application’s requirements and the total available DDR RAM.

  3. Extending the Cortex M4 RAM: To extend the Cortex M4 RAM, you would need to adjust the memory partitioning settings to allocate more DDR RAM to the M4 core. This involves modifying the Device Tree or U-Boot environment settings to increase the size of the memory region reserved for the M4 core. Keep in mind that increasing the memory allocation for the M4 core will decrease the available memory for the Linux system, so you’ll need to balance the requirements of both cores. Additionally, ensure that the memory regions allocated to the M4 do not overlap with critical Linux system resources or other reserved areas.

When making these adjustments, it’s crucial to refer to the i.MX 8X documentation for detailed information on memory mapping and to ensure that the changes to memory partitioning do not conflict with other system requirements. Also, testing the system thoroughly after making these changes is essential to ensure that both the M4 core and the Linux system operate reliably with the new memory configuration.

Best regards,
Toradex AI Assistant

Please, also check if these links can help you solve your problem:

Cortex-M and Memory Areas on Toradex SoMs | Toradex Developer Center.

Hy,
Am using device tree from toradex repository,

can you please tell where i need to edit to specify M4 cortex DDR RAM starting address and size .

Regards,
Ouseppachan CR

Hi @Ouseppachan ,
We are looking into it, allow us some time

Hi @sahil.tx ,
For M4 core am following a linker script MIMX8QX6xxxxx_cm4_ddr_ram.ld , with this script am unable to boot both linux and M4 core at a time. what changes i need to do to make this work?

regards,
Ouseppachan CR

Hi @Ouseppachan ,
How you are using this linker script and for what purpose?
Do you mean that you are trying to compile m4 binary based on this linker script( MIMX8QX6xxxxx_cm4_ddr_ram.ld) ?
If this is the case then you can simply run build_all.sh and use the binary generated from ddr_debug/ddr_release folder

Hy @sahil.tx ,
I tried build with build_all.sh exactly what you have said.
I found 3 linker files in sample program. MIMX8QX6xxxxx_cm4_ram.ld is working very fine but here we have max 192kb memory, s that i tried with MIMX8QX6xxxxx_cm4_ddr_ram.ld but this is making entire system continously rebooting . And MIMX8QX6xxxxx_cm4_ddr_ram.ld is working from uboot where linux is not getting booted.

regards,
Ouseppachan

Hi @Ouseppachan ,
What BSP version you are using?

Hi @sahil.tx ,

I am using torizon-core-docker-colibri-imx8x-Tezi_5.7.2+build.20.tar.

Hi @Ouseppachan ,
I am testing the demos with the same setup and trying to repduce the issue

Hi @sahil.tx ,

So how its going. I hope you understood my issue…

Regards,
Ouseppachan