I set the colibri imx6 to use the “EDT-WVGA” display setting. I attached an oscilloscope probe to LCD_PCLK_WR on the eval board. While the clock frequency on average is correct, there seems to be some “jitter” in the signal. Attached is an oscilloscope image with persistence on. You can see there are two different frequencies. I would expect this signal to much more consistent. Any ideas why this is happening and how to fix it?
I have created a custom carrier board and I see the same thing. On this custom carrier I am sending the display signals to a serializer. The serializer is trying to lock onto the pixel clock but I think this is messing it up.
The IPU is able to generate a pixelclock with a non integer divider resulting in a average frequency at the desired value but individual pulses do not all have the same length.
You would need to choose a timing which results in an integer divider value.
E.g. I can see the effect you describe when I use the “EDT-WVGA” timing in vidargs, I can not see it when I use “800x480M@60”.
There are several reports of this also on NXP’s community website, e.g. here.
The following file on the running module can help in checking currently used parent clocks and dividers: /sys/kernel/debug/clk/clk_summary
