Colibri i.MX7, openOCD and hardware break points

Technical Support
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1

Hi !
Following my post on colibri i.MX7 (see Using OpenOCD with imx7/colibri - Technical Support - Toradex Community) I can now reset and halt my A7 using the jtag connexion, early enough to debug my code (thanks again !).

However, when I’m trying to set a hardware break point to reach my actual issue, I get the following error

no hardware breakpoint available
can't add breakpoint: resource not available
Failure setting breakpoint, the same address(IVA) is already used

Here is a full log of my attempt:

# OpenOCD terminal
$ sudo openocd -f tcl/interface/ftdi/dp_busblaster.cfg -f tcl/board/nxp_imx7sabre.cfg
Open On-Chip Debugger 0.10.0+dev-00403-g3737dd6 (2018-04-23-09:42)
Licensed under GNU GPL v2
For bug reports, read
        http://openocd.org/doc/doxygen/bugs.html
Info : If you need SWD support, flash KT-Link buffer from https://github.com/bharrisau/busblaster
and use dp_busblaster_kt-link.cfg instead
adapter speed: 1000 kHz
srst_only separate srst_gates_jtag srst_push_pull connect_deassert_srst
adapter_nsrst_assert_width: 100
adapter_nsrst_delay: 10
Info : Listening on port 6666 for tcl connections
Info : Listening on port 4444 for telnet connections
Info : clock speed 1000 kHz
Info : JTAG tap: imx7.cpu tap/device found: 0x5ba00477 (mfg: 0x23b (ARM Ltd.), part: 0xba00, ver: 0x5)
Info : imx7.cpu_a7.0: hardware has 6 breakpoints, 4 watchpoints
Info : Listening on port 3333 for gdb connections
Info : Listening on port 3334 for gdb connections
Info : accepting 'telnet' connection on tcp/4444
Error: Target not halted
pc (/32): 0x00000000
Info : JTAG tap: imx7.cpu tap/device found: 0x5ba00477 (mfg: 0x23b (ARM Ltd.), part: 0xba00, ver: 0x5)
Error: Debug regions are unpowered, an unexpected reset might have happened
Error: JTAG-DP STICKY ERROR
Info : Deferring arp_examine of imx7.cpu_a7.1
Info : Use arp_examine command to examine it manually!
Info : Deferring arp_examine of imx7.cpu_m4
Info : Use arp_examine command to examine it manually!
Warn : imx7.cpu_a7.0: ran after reset and before halt ...
Warn : imx7.cpu_a7.1: ran after reset and before halt ...
Info : imx7.cpu_a7.0 rev 5, partnum c07, arch f, variant 0, implementor 41
Info : imx7.cpu_a7.0 cluster 0 core 0 multi core
target halted in Thumb state due to debug-request, current mode: Supervisor
cpsr: 0x2000a4f3 pc: 0x00920aea
Info : imx7.cpu_a7.0 rev 5, partnum c07, arch f, variant 0, implementor 41
MMU: disabled, D-Cache: disabled, I-Cache: enabled
memory bus access delay set to 0 tck
pc (/32): 0x00920AEA
Error: Invalid command argument
length option value ('hw') is not valid

Info : no hardware breakpoint available
Error: can't add breakpoint: resource not available
Error: Failure setting breakpoint, the same address(IVA) is already used

Info : no hardware breakpoint available
Error: can't add breakpoint: resource not available
Error: Failure setting breakpoint, the same address(IVA) is already used

# Telnet terminal
$ telnet localhost 4444                                                                                                                                                               
Trying 127.0.0.1...
Connected to localhost.
Escape character is '^]'.
Open On-Chip Debugger
> reg pc
Target not halted
pc (/32): 0x00000000
> reset init
JTAG tap: imx7.cpu tap/device found: 0x5ba00477 (mfg: 0x23b (ARM Ltd.), part: 0xba00, ver: 0x5)
Debug regions are unpowered, an unexpected reset might have happened
JTAG-DP STICKY ERROR
Deferring arp_examine of imx7.cpu_a7.1
Use arp_examine command to examine it manually!
Deferring arp_examine of imx7.cpu_m4
Use arp_examine command to examine it manually!
imx7.cpu_a7.0: ran after reset and before halt ...
imx7.cpu_a7.1: ran after reset and before halt ...
imx7.cpu_a7.0 rev 5, partnum c07, arch f, variant 0, implementor 41
imx7.cpu_a7.0 cluster 0 core 0 multi core
target halted in Thumb state due to debug-request, current mode: Supervisor
cpsr: 0x2000a4f3 pc: 0x00920aea
imx7.cpu_a7.0 rev 5, partnum c07, arch f, variant 0, implementor 41
MMU: disabled, D-Cache: disabled, I-Cache: enabled
memory bus access delay set to 0 tck
> reg pc
pc (/32): 0x00920AEA
> bp 0x00920AEA hw
Invalid command argument
length option value ('hw') is not valid

> bp 0x00920AEA 4 hw
no hardware breakpoint available
can't add breakpoint: resource not available
Failure setting breakpoint, the same address(IVA) is already used

> bp 0x00920AEA 1 hw
no hardware breakpoint available
can't add breakpoint: resource not available
Failure setting breakpoint, the same address(IVA) is already used

Openocd advertizes 6 breakpoints, but I can’t manage to set even one. How should I do it ?
My configuration is the one described in the previous post, patched with @dominik.tx answers

2

I’ve tried it:

> reset halt
JTAG tap: imx7.dap tap/device found: 0x5ba00477 (mfg: 0x23b (ARM Ltd.), part: 0xba00, ver: 0x5)
Debug regions are unpowered, an unexpected reset might have happened
JTAG-DP STICKY ERROR
imx7.cpu_a7.0: ran after reset and before halt ...
target halted in Thumb state due to debug-request, current mode: Supervisor
cpsr: 0x400000f3 pc: 0x00000274
imx7.cpu_a7.0 rev 5, partnum c07, arch f, variant 0, implementor 41
MMU: disabled, D-Cache: disabled, I-Cache: enabled
> bp 0x8fd1aac4 4 hw
breakpoint set at 0x8fd1aac4
> bp
Breakpoint(IVA): 0x8fd1aac4, 0x4, 1
> resume
target halted in Thumb state due to breakpoint, current mode: Supervisor
cpsr: 0x200000f3 pc: 0x8fd1aac4
imx7.cpu_a7.0 rev 5, partnum c07, arch f, variant 0, implementor 41
MMU: enabled, D-Cache: enabled, I-Cache: enabled

I have a bit more stuff commented out in my config file.

# disable internal reset-assert handling to¬
 # allow reset-init to work¬
 #$_TARGETNAME.0 configure -event reset-assert ""¬
 #$_TARGETNAME.1 configure -event reset-assert ""¬
 #$_TARGETNAME_2 configure -event reset-assert ""¬
 ¬
 #$_TARGETNAME.0 configure -event reset-init {¬
 #    global _CHIPNAME¬
 #    imx7_disable_wdog¬
 #    imx7_uart_dbgconf¬
 # apply_dcd¬
 #    imx7dap.dap memaccess 0¬
 #}¬
 ¬
 #target smp $_TARGETNAME.0 $_TARGETNAME.1¬
3

If I comment out the three configure line, it doesn’t work, but using reset halt instead of reset init seems to leave enough bp for me to work with. Thank you once again

4

Not an answer, but feedback from the nice guys of #openocd:

I think I know what happens: in your config you have two cores defined, and you enable SMP handling for them. When you add a hardware breakpoint you need to do that after both cores were examined properly, as
the SMP-specific code needs to enable same hw breakpoints on all cores.

The important part in @dominik.tx 's answer is the commenting of the smp configuration. I did a few test following this feedback that confirm this.

5

Neither bootrom nor uboot enables second core, so removing smp makes sense. It’s good to know that enabling smp and having un-examined cores will prevent hw breakpoints creation.