where can I find information about the possible settings for CLK-EXTCLK2
You should be able to receive the TRM from Nvidia by registering on this page:
Hard to say what is missing. However, do you use an external Pull Up resistor? If not you should activate the internal one 0x80 in PINMUX_AUX_CLK2_OUT_0. Also maybe try to reduce the clock a bit by writing a divisor into CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2_0. It could be that the frequency is just too high.
Sorry it would be 0x40. Why do you think Pull Up only works in input mode? Where did they write that? If it really doesn’t work then you would have to add an external Pull Up, I guess.
After setting 0x80 in PINMUX_AUX_CLK2_OUT_0 blocks changes in this registry.
Pull Up resistor only works in input mode.
The frequency division does not change anything
What else should be set to get the clock signal on CLK-OUT2?
CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2_0 (0x600063f0) 0x60000000 CLK_RST_CONTROLLER_CLK_ENB_V_SET_0 (0x60006440) 0x02000000 (SET_CLK_ENB_EXTPERIPH2) PINMUX_AUX_CLK2_OUT_0 (0x70003068) 0x00
but no signal clock on pad CLK2_OUT. What else should I set?
I set 0x40 in PINMUX_AUX_CLK2_OUT_0 - nothing changed.
I connected an external Pull Up resistor - nothing changed.
There is no external pull-up resistor on the evaluation board - SODIMM_75
The question is how to unlock the clock?
Unfortunately we also don’t have a clear answer to that… You code doesn’t look wrong. Maybe the PLLA clock out is not enabled? Can you check/modify CLK_RST_CONTROLLER_PLLA_OUT_0 for that? Maybe you can also check if it works with another clock source?
The register CLK_RST_CONTROLLER_PLLA_OUT_0 has a value 0x2803
Changing the signal source ( CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2_0 PLLA_OUT 0x0f0) does not change anything
Can you indicate sample register settings to get the clock signal on the pad SODIMM_75?
Hi @Darek ,
There is another register that needs to be changed. The External Clock will only start clocking on request by default (depending on the level of EXTREQ pin). But this can be changed to ignore the clock request pin.
Check APBDEV_PMC_CLK_OUT_CNTRL_0 in the T30 Reference manual.
You need to set CLK2_FORCE_EN to 1
In this register you can also set some other options, like running directly from OSC frequency.
let me know it this finally helps.
Record to register (APBDEV_PMC_CLK_OUT_CNTRL_0 0x700001A8) is blocked.
I always read 0x00000000.(Reg Access Tool v1.5)
How can it be unblocked?
Hi @Darek ,
The Base address for PMC is 0x7000e400, so the offset you’re looking for is 0x7000E5A8
Let me know if it works
problem has been solved.
Glad i could help