Clarification on MOSI and MISO pins in SPI

Meenakshy · October 31, 2025, 11:00am

Hi Team,

I created an overlay to enable SPI3 for connecting my 3.5” MSP3520 TFT Display.
Hereby adding my overlay file,

🐧 root @GalaxyBook/home/Meenakshy/Projects/SPI_TFT_Display/tcbdir: cat device-trees/overlays/verdin-am62_msp3520_tft_display_spi3_overlay.dts
/dts-v1/;
/plugin/;

#include "../../linux/arch/arm64/boot/dts/ti/k3-pinctrl.h"
#include "../../linux/include/dt-bindings/interrupt-controller/irq.h"
#include "../../linux/include/dt-bindings/gpio/gpio.h"

/ {
        compatible = "toradex,verdin-am62";
};

/* Disable HDMI using the actual node name */
&{/hdmi-connector} {
    status = "disabled";
};

/* Disable the HDMI bridge on I2C1 */
&{/bus@f0000/i2c@20010000/hdmi@48} {
    status = "disabled";
};

/* Remove the conflicting HPD GPIO pin configuration */
&main_pmx0 {
    /delete-node/ main-gpio1-17-default-pins;
};

/* Remove connector configuration that uses PIN113 */
&{/connector} {
    status = "disabled";
};

/* Verdin SPI_3 pins */
&main_pmx0 {
        spi3_pins_default: spi3-default-pins {
                pinctrl-single,pins = <
                        AM62X_IOPAD(0x01bc, PIN_OUTPUT, 0) /* (A14) SPI0_CLK - SODIMM_19 */
                        AM62X_IOPAD(0x01b4, PIN_OUTPUT, 0) /* (A13) SPI0_CS0 - SODIMM_15 */
                        AM62X_IOPAD(0x01b8, PIN_OUTPUT, 0) /* (C13) SPI0_CS1 - SODIMM_16 */
                        AM62X_IOPAD(0x01c4, PIN_OUTPUT, 0) /* (B14) SPI0_D1 - MOSI - SODIMM_161 */
                        AM62X_IOPAD(0x01c0, PIN_INPUT, 0) /* (B13) SPI0_D0 - MISO - SODIMM_66 */
                >;
        };
};

&epwm1 {
        status = "disabled";
};

&epwm0 {
        status = "disabled";
};

/* Verdin SPI_0 - Enable for LCD */
&main_spi0 {
        pinctrl-names = "default";
        pinctrl-0 = <&spi3_pins_default>;
        status = "okay";
        ti,spi-num-cs = <2>;

        #address-cells = <1>;
        #size-cells = <0>;
    
        msp3520_display@0 {
                compatible = "rohm,dh2228fv";
                reg = <0>;
                spi-max-frequency = <10000000>;
                status = "okay";
        };

        msp3520_touch@1 {
                compatible = "ti,ads7846";
                reg = <1>;
                spi-max-frequency = <1000000>;
                status = "okay";

                interrupt-parent = <&mcu_gpio0>;
                interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
                pendown-gpio = <&mcu_gpio0 4 GPIO_ACTIVE_LOW>;

                ti,x-plate-ohms = /bits/ 16 <180>;
                ti,pressure-max = /bits/ 16 <255>;

                wakeup-source;
        };
};
🐧 root @GalaxyBook/home/Meenakshy/Projects/SPI_TFT_Display/tcbdir:

In Toradex pinout-designer tool, we can use SODIMM_161 and SODIMM_66 as MOSI and MISO for SPI3.

So, I configured in my overlay as SODIMM_161 as PIN_OUTPUT, which is MOSI and SODIMM_66 as PIN_INPUT, which is MISO. My display got worked when my LCD’s MOSI is connected to SODIMM_161 (MOSI).

After that, I reversed the configuration. I configured SODIMM_161 as PIN_INPUT, which is MISO and SODIMM_66 as PIN_OUTPUT, which is MOSI. My display should work when I connect the MOSI pin of my LCD to SODIMM_66(MOSI). But my display got worked, when I connected to SODIMM_161 (MISO).
In overlay I made a small change,

/* Verdin SPI_3 pins */
&main_pmx0 {
        spi3_pins_default: spi3-default-pins {
                pinctrl-single,pins = <
                        AM62X_IOPAD(0x01bc, PIN_OUTPUT, 0) /* (A14) SPI0_CLK - SODIMM_19 */
                        AM62X_IOPAD(0x01b4, PIN_OUTPUT, 0) /* (A13) SPI0_CS0 - SODIMM_15 */
                        AM62X_IOPAD(0x01b8, PIN_OUTPUT, 0) /* (C13) SPI0_CS1 - SODIMM_16 */
                        AM62X_IOPAD(0x01c4, PIN_INPUT, 0) /* (B14) SPI0_D1 - MISO - SODIMM_161 */
                        AM62X_IOPAD(0x01c0, PIN_OUTPUT, 0) /* (B13) SPI0_D0 - MOSI - SODIMM_66 */
                >;
        };
};

What is the reason behind this strange behavior?

Thanks & Regards,
Meenakshy

ToradexAI · October 31, 2025, 11:01am

Hi, I’m the Toradex AI Assistant.

I might make mistakes or occasionally get you wrong. Our support team will step in if needed.

Understanding SPI Pin Configuration Behavior

The behavior you’re experiencing relates to how the AM62 SoC’s SPI controller handles the SPI0_D0 and SPI0_D1 pins and their roles in SPI communication.

Pin Function Analysis

Looking at your overlay configuration, you’re using the main_spi0 controller with these pin assignments(1):

SPI0_CLK (SODIMM 19) - Clock signal
SPI0_CS0 (SODIMM 15) - Chip Select 0
SPI0_CS1 (SODIMM 16) - Chip Select 1
SPI0_D0 (SODIMM 66) - Data line 0
SPI0_D1 (SODIMM 161) - Data line 1

The Root Cause

The key issue is in understanding the hardware-level pin functions versus the logical MOSI/MISO assignment:

SPI0_D0 is typically the primary data line for the SPI controller
SPI0_D1 is typically the secondary data line for the SPI controller

When you configure the SPI controller in master mode, the controller’s internal logic determines which physical pin serves as MOSI (Master Out, Slave In) based on the controller’s design, not just the PIN_INPUT/PIN_OUTPUT direction settings.

Why Your Display Works on SODIMM 161

Your display consistently works when connected to SODIMM 161 (SPI0_D1) because:

The AM62’s SPI0 controller likely uses SPI0_D1 as its MOSI output in master mode
The PIN_INPUT/PIN_OUTPUT settings in your pinmux configuration affect the pin’s electrical characteristics but don’t override the controller’s internal signal routing
The SPI controller’s hardware design determines the actual signal direction regardless of your pinmux direction settings

Hardware Connection

Connect your MSP3520 display as follows:

Display MOSI → SODIMM 161 (SPI0_D1)
Display MISO → SODIMM 66 (SPI0_D0)
Display SCK → SODIMM 19 (SPI0_CLK)
Display CS → SODIMM 15 (SPI0_CS0)

This aligns with the AM62 SPI controller’s hardware design and should provide reliable communication with your display.

Best regards, Toradex AI Assistant.

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lucas_az.tx · November 3, 2025, 12:23pm

Hi @Meenakshy!

The answer from the Toradex AI looks reasonable. Did it clear up your doubt?

Best regards.

Meenakshy · November 4, 2025, 5:18am

Hi Lucas,

Thank you for your response to my query.

I would appreciate a more detailed answer — specifically, is it possible to view the internal logic of the AM62’s SPI0 controller to help address my issue?