On page 2564 of the reference manual for the i.MX7D section 9.7.4 tells that there are 4 configurations supported for the Chip Select mapping. However, there are 6 CSnGCR1 registers, each woth a CSEN field to enable a chip select.
Are there 2 additional Chip Select registers for compatibility issues (so the first 4 CSEN mapping each of the 4 CS) or there is something else I missed?
We need to configure the bus to Multiplexed mode, to read and write a byte in a single Chip Select cycle. We managed to configure the writing, but when we try reading in the same way the i.MX repeats the same cycle for the 7 next addresses.
The configuration is:
EIM_CSnGCR1 = 0x00F34439;
EIM_CSnGCR2 = 0x00001002;
EIM_CSnRCR1 = 0x0F010300;
EIM_CSnRCR2 = 0x00000019;
EIM_CSnWCR1 = 0x0F080CC0;
Could a change to EIM_DCR make the reading work in a single cycle?
Yes there are 6 CSnGCR1 registers listed EIM memory map table. Unfortunately I can’t explain this. Since EIM configuration is not Toradex specific I’d recommend to use NXP community for such questions.