Change drive strength of LVDS display

Technical Support
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1

Hi,

We’re experiencing some EMC issues with a display connected to our i.MX8 board. We are using LVDS screen with touch controls. I’ve read that it’s possible to improve EMC performance by adjusting the drive strength through a device tree overlay. However, I’m having trouble identifying which pins need to be configured and how to do this on the i.MX8 board.

In our system, we use iMX8QM. We designed a custom board based on the Apalis ixora Evaluation Board V1.1, which uses the imx8qm SOM.

Also, we want to look for an option to enable spread spectrum clock for display clock.
And could you guide me on where to find documentation about the pins that need configuration? Additionally, where can I find information on their names and references?

2

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To address your EMC issues with the LVDS display on your i.MX8QM-based custom board, you can indeed adjust the drive strength through the device tree overlay. Here’s a step-by-step guide to help you with this:

1. Identifying the Pins

First, you need to identify the LVDS pins that are used in your design. The i.MX8QM reference manual and the Apalis iMX8 datasheet will be helpful in identifying these pins. Typically, LVDS pins are labeled with names like LVDS0_TX0_P, LVDS0_TX0_N, etc.

2. Configuring the Device Tree

In the device tree, you can configure the drive strength, slew rate, and speed for these pins. Here’s an example of how you might configure these settings in the device tree:

&lvds0 {
    pinctrl-names = "default";
    pinctrl-0 = <&pinctrl_lvds0>;
};

pinctrl_lvds0: lvds0grp {
    fsl,pins = <
        MX8QM_IOMUXC_LVDS0_TX0_P_LVDS0_TX0_P 0x1c6
        MX8QM_IOMUXC_LVDS0_TX0_N_LVDS0_TX0_N 0x1c6
        // Add other LVDS pins here
    >;
};

In the above example, 0x1c6 is a placeholder for the pad control settings. You will need to replace it with the appropriate settings for drive strength, slew rate, and speed. Refer to the NXP/Freescale application note AN5078 for detailed information on these settings.

3. Enabling Spread Spectrum Clocking

To enable spread spectrum clocking on the DDR interface, you will need to customize U-Boot and ATF. Here’s a brief outline of the steps:

  1. Setup Yocto Project Environment: Follow the instructions in the Build a Reference Image with Yocto Project/OpenEmbedded article to set up your development environment.

  2. Customize U-Boot: Modify the U-Boot source code to enable spread spectrum clocking. You will need to locate the appropriate configuration settings in the U-Boot source code and enable spread spectrum clocking.

  3. Customize ATF

3

Hi,
Could I get an answer more related to Yocto with kernel 5.15 for imx8qm.
Looks like device tree does not have lvds registers except

In a file “imx8-apalis-v1.1.dtsi” :

/* Apalis BKL1_PWM */
pinctrl_pwm_bkl: pwmbklgrp {
fsl,pins =
<IMX8QM_LVDS1_GPIO00_LVDS1_PWM0_OUT 0x00000020>;
};

which is in high drive strength in its last bit definition.
0b - high drive strength
1b - low drive strength

Would this help on changing display drive strength on LVDS?

Best regards
Ahmet

4

Hi, @ahmetg!

I checked Apalis iMX8QM device tree and you were right, it is not possible to change the drive strength of LVDS data pins, and, as far as I understand, it would not be helpful to change the drive strength of control pins.

As you are using a custom board, I would recommend reviewing the board layout and design, following our Carrier Board Design Guides article. In this article, you can find our Carrier Board Layout Guide, which has hints and good practices about board development.

The cable could be also the source of EMC, it would be reasonable to check it.

Best regards.
Lucas Azeituno

5

Thanks a lot Lucas, for an answer.

Best regards
Ahmet