Can't make GPIOs working on IMX6ULL Torizon

Technical Support
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1

We want to use the SODIMM 33, 35, 45, 49, 53, 59 and 79 pins on a Colibri IM6XULL 1 Gb eemc / Torizon

For that, we buil and deploy a new device-tree, using torizoncore-builder and the “Approach 1“ of “Device Tree Overlays on Torizon | Toradex Developer Center

We can find our overlay in “/proc/device-tree/chosen/overlays” and see the expected GPIOs via “/sys/kernel/debug/gpio”.

But when we change the values of the GPIOs, only SODIMM45 change its electrical level. All the other ones stay unchanged.

Could you help us to make it working ?

tcbuild.yaml (585 Bytes)

Mod200F_imx6ULL.dtsi (1.9 KB)

Mod200F_imx6ULL.dts (289 Bytes)

Thanks for your help

2

Hi, I’m the Toradex AI Assistant.

I might make mistakes or occasionally get you wrong. Our support team will step in if needed.

GPIO Configuration Issue on Colibri iMX6ULL

I can help troubleshoot your GPIO configuration issue. Since you’re working with specific SODIMM pins and device tree overlays, I need to understand your setup better to provide accurate guidance.

First, Let Me Confirm Your Configuration

To provide the most accurate assistance, could you please specify which version of Torizon OS you’re running? You can check this by running tdx-info on your device, which will provide detailed information about your system configuration(1). You can find more details about this command at Getting Device Information with Tdx-Info | Toradex Developer Center.

Initial Analysis

Based on your description, you’re using TorizonCore Builder with Approach 1 to customize device tree overlays for Colibri iMX6ULL(1). The fact that only SODIMM 45 responds while others remain unchanged suggests there may be pin muxing conflicts or configuration issues with the specific pins.

Pin Configuration Reference

For the Colibri iMX6ULL, pin configurations are controlled through the Pad Control Register and Pad Mux Register(2). Each pin has specific alternate functions that need to be properly configured in the device tree.

Next Steps

Once you provide your Torizon OS version, I can give you specific guidance on:

  1. Pin Muxing Verification: Ensuring the pins are correctly configured for GPIO function
  2. Device Tree Overlay Structure: Reviewing the overlay syntax for your specific OS version
  3. Conflict Resolution: Identifying potential conflicts with other peripherals

The TorizonCore Builder tool supports device tree customization through configuration files, and the build process should compile your overlays correctly(1)(3).

Please share your Torizon OS version so I can provide more targeted assistance for your specific setup.

Best regards, Toradex AI Assistant.

Did you like my answer? :+1: :-1:

If I answered your question, please tick the “Solution” checkbox.

For follow-up questions to me, please use @ToradexAI in your post.

3

the tdx-info results is :

4

GPIO Configuration Issue on Colibri iMX6ULL

Thank you for providing the system information. You’re running Torizon OS 7.5.0-devel-202512-build.15 with PREEMPT_RT on a Colibri iMX6ULL 1GB (eMMC) on the Evaluation Board V3 (1). This helps me provide more targeted assistance for your GPIO configuration issue.

Understanding Your Setup

Your device tree overlay approach using TorizonCore Builder is correct (2). The fact that your overlay appears in /proc/device-tree/chosen/overlays and the GPIOs are visible in /sys/kernel/debug/gpio indicates that the overlay is being applied successfully (3).

Troubleshooting the GPIO Issue

Since only SODIMM 45 responds while the other pins (SODIMM 33, 35, 49, 53, 59, 79) remain unchanged, this typically indicates one of these issues:

1. Pin Muxing Conflicts

The pins may be claimed by other peripherals or have incorrect mux settings. For Colibri iMX6ULL, you need to ensure each pin is properly configured for GPIO function in your device tree overlay (3).

2. Device Tree Overlay Configuration

Your overlay structure should follow the proper format for Torizon OS 7.x. The customization should be applied through the TorizonCore Builder configuration file (2).

Configuration File Structure

Based on your Torizon OS version, your tcbuild.yaml should include the device tree overlay configuration like this (3):

customization:
  device-tree:
    include-dirs:
    # Folder that contains common kernel header files like gpio.h
      - linux/include
    # Folder containing overlays included by your overlay file
      - device-trees/overlays
    overlays:
      add:
      # Your overlay to be applied
        - device-trees/overlays/Mod200F_imx6ULL.dts

(3)

Next Steps for Resolution

  1. Verify Pin Availability: Check that the pins you’re trying to use aren’t already claimed by other device tree nodes
  2. Review Overlay Syntax: Ensure your device tree overlay follows the correct format for your specific Torizon OS version
  3. Check Pin Muxing: Verify that each pin is properly configured for GPIO function in your overlay

Since you’ve attached your configuration files, the issue is likely in the device tree overlay implementation rather than the TorizonCore Builder setup itself (2).

Could you share the contents of your Mod200F_imx6ULL.dts and Mod200F_imx6ULL.dtsi files? This will help me identify the specific configuration issue preventing the other GPIO pins from responding properly.

Best regards, Toradex AI Assistant.

Did you like my answer? :+1: :-1:

If I answered your question, please tick the “Solution” checkbox.

For follow-up questions to me, please use @ToradexAI in your post.

5

The Mod200F_imx6ULL.dts and MOD200F_imx6ULL.dtsi were shared in my first post

6

And we can’t see any problems when we control your specific guidances…

7

No suggestion ??

Help would be greatly appreciate …

8

Hi @Jch!

This is usually caused by the device tree configuration. To use these as GPIOs, you must disable any other node that may use them (either as GPIO or another function). Make sure to use the right device tree (here you can find how to deploy a device tree to a running device) as well as the appropriate overlay (here to learn how to deploy it).

Additionally, how are you trying to control these GPIOs? Please refer to this article to learn how we support/recommend managing GPIOs on Torizon.

I also noticed that you opened another thread with the same subject, so I’ll close the other one and proceed with the assistance here.

Best regards.

9

Hi Lucas,

Thanks for your return. But we had already checked all the data given in the links you give us.

All show that our overlay is right deployed on the board. We also control the GPIOs the same way that your article explain. But the electrical levels remain unchanged…

If we omit to disable one function which could avoid these pins to act as GPIOS, we can’t find it, despite we tried to find it …

Could you check the files I attached in my first post and explain us what is wrong ??

Thanks for your help.

Best regards.

10

First of all, you should not use gpio-keys for this purpose. It is intended for GPIO inputs (buttons/switches). The driver requests the GPIOs as inputs and reports events via /dev/input/eventX, so it will not allow you to drive them as outputs.

Also, as Lucas mentioned, you must disable any other node that may use these pins (either as GPIOs or for an alternate function).
so your DTSI should looks like:

#include "imx6ull-colibri-emmc-nonwifi.dtsi"

/ {
    model = "iMX6ULL 1GB (eMMC) on MOD200F board";
    compatible = "toradex,colibri-imx6ull-emmc-nonwifi", "fsl,imx6ull";

    /* Apply pinmux group globally */
    pinctrl-names = "default";
    pinctrl-0 = <&pinctrl_gpio_user>;
};

&iomuxc {
    pinctrl_gpio_user: gpio_user_grp {
        fsl,pins = <
            MX6UL_PAD_UART1_TX_DATA__GPIO1_IO16    0x3038  /* SODIMM 33 */
            MX6UL_PAD_UART1_RX_DATA__GPIO1_IO17    0x3038  /* SODIMM 35 */
            MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04   0x10B0  /* SODIMM 73 */
            MX6UL_PAD_SD1_DATA1__GPIO2_IO19        0x10B0  /* SODIMM 49 */
            MX6UL_PAD_SD1_DATA3__GPIO2_IO21        0x10B0  /* SODIMM 53 */
            MX6UL_PAD_NAND_WP_B__GPIO4_IO11        0x3038  /* SODIMM 59 */
            MX6UL_PAD_CSI_DATA02__GPIO4_IO23       0x3038  /* SODIMM 79 */
            MX6UL_PAD_CSI_DATA03__GPIO4_IO24       0x3038  /* SODIMM 97 */
            MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01     0x3038  /* SODIMM 45 */
        >;
    };
};

/* Disable peripherals that would otherwise own those pads */
&uart1 {
    status = "disabled";
};

&usdhc1 {
    status = "disabled";
};
11

Thanks Alex,

We made the changes you advise us.

But … still not working …Only SODIMM45 change its electrical level. All the other ones stay unchanged.

12

Still no help ?? Would be greatly appreciate …