I’m using the Colibri iMX7D 512 module & Aster board, as purchased from Toradex. The SoC has software as programmed by Toradex before shipping. (or Colibri eval board, same result)
I’m trying to do work on M4 core, with hardware debugger with JTAG interface. I’m using Segger J-Link Plus, and latest soft package they supply - V6.20i.
I’m testing on example project(s) as provided by NXP, and, targeted for SABRE iMX7D board. But this is not relevant for my question, see below.
The problem I have is that the debugger cannot connect to the M4 or A7 core _if Linux has booted _ (don’t know at which stage).
I can successively connect to M4 or A7 cores iff only u-boot is running and before it starts Linux.
So for example
JLinkExe -device MCIMX7D7_A7_0 -autoconnect 1 -if JTAG -speed 4000 -JTAGConf -1,-1
JLinkExe -device Cortex-M4 -autoconnect 1 -if JTAG -speed 4000 -JTAGConf -1,-1
Both cases connect, and then I can do setup required to upload the M4 code and run & debug it. Tested with “hello_world” FreeRTOS based example.
But things break after Linux has started. It is not possible to connect anymore to either core.
See below messages / errors:
A7
JLinkExe -device MCIMX7D7_A7_0 -autoconnect 1 -if JTAG -speed 4000 -JTAGConf -1,-1
SEGGER J-Link Commander V6.20i (Compiled Nov 17 2017 17:33:21)
DLL version V6.20i, compiled Nov 17 2017 17:33:15
Connecting to J-Link via USB...O.K.
Firmware: J-Link V10 compiled Nov 14 2017 11:13:00
Hardware version: V10.00
S/N: 600000226
License(s): RDI, FlashBP, FlashDL, JFlash, GDB
VTref = 3.373V
Device "MCIMX7D7_A7_0" selected.
Connecting to target via JTAG
***************************************************
J-Link script: iMX7D Cortex-A7_0 core J-Link script
***************************************************
TotalIRLen = 4, IRPrint = 0x01
JTAG chain detection found 1 devices:
#0 Id: 0x5BA00477, IRLen: 04, CoreSight JTAG-DP
**************************
WARNING: Identified core does not match configuration. (Found: None, Configured: Cortex-A7)
**************************
***************************************************
J-Link script: iMX7D Cortex-A7_0 core J-Link script
***************************************************
TotalIRLen = 4, IRPrint = 0x01
JTAG chain detection found 1 devices:
#0 Id: 0x5BA00477, IRLen: 04, CoreSight JTAG-DP
****** Error: Could not power up debug port: Control/Status register reads 40000003
***************************************************
J-Link script: iMX7D Cortex-A7_0 core J-Link script
***************************************************
TotalIRLen = 4, IRPrint = 0x01
JTAG chain detection found 1 devices:
#0 Id: 0x5BA00477, IRLen: 04, CoreSight JTAG-DP
***************************************************
J-Link script: iMX7D Cortex-A7_0 core J-Link script
***************************************************
TotalIRLen = 4, IRPrint = 0x01
JTAG chain detection found 1 devices:
#0 Id: 0x5BA00477, IRLen: 04, CoreSight JTAG-DP
Cannot connect to target.
M4
JLinkExe -device Cortex-M4 -autoconnect 1 -if JTAG -speed 4000 -JTAGConf -1,-1
SEGGER J-Link Commander V6.20i (Compiled Nov 17 2017 17:33:21)
DLL version V6.20i, compiled Nov 17 2017 17:33:15
Connecting to J-Link via USB...O.K.
Firmware: J-Link V10 compiled Nov 14 2017 11:13:00
Hardware version: V10.00
S/N: 600000226
License(s): RDI, FlashBP, FlashDL, JFlash, GDB
VTref = 3.373V
Device "CORTEX-M4" selected.
Connecting to target via JTAG
TotalIRLen = 4, IRPrint = 0x01
JTAG chain detection found 1 devices:
#0 Id: 0x5BA00477, IRLen: 04, CoreSight JTAG-DP
Scanning AP map to find all available APs
AP[0]: Stopped AP scan as end of AP map seems to be reached
Iterating through AP map to find AHB-AP to use
Scanning AP map to find all available APs
AP[0]: Stopped AP scan as end of AP map has been reached
Iterating through AP map to find AHB-AP to use
****** Error: Bad JTAG communication: Write to IR: Expected 0x1, got 0xF (TAP Command : 10) @ Off 0x5.
Could not find core in Coresight setup
Cannot connect to target.
Another A7 attempt
Connecting to target via JTAG
***************************************************
J-Link script: iMX7D Cortex-A7_0 core J-Link script
***************************************************
TotalIRLen = 4, IRPrint = 0x01
JTAG chain detection found 1 devices:
#0 Id: 0x5BA00477, IRLen: 04, CoreSight JTAG-DP
CoreSight AP[0]: 0x04770001, AHB-AP
CoreSight AP[1]: 0x04770002, APB-AP
CoreSight AP[2]: 0x0477000F, Unknown-AP (Reserved)
CoreSight AP[3]: 0x0477000F, Unknown-AP (Reserved)
CoreSight AP[4]: 0x04770001, AHB-AP
ROMTbl[0][0]: CompAddr: 80040000 CID: B105100D, PID:00-00080000 ROM Table
Invalid ROM table component ID 0x100DD3D3 @ 0x80040FF0 (expected 0xB105100D). Trying again at alternative offset.
***************************************************
J-Link script: iMX7D Cortex-A7_0 core J-Link script
***************************************************
TotalIRLen = 4, IRPrint = 0x01
JTAG chain detection found 1 devices:
#0 Id: 0x5BA00477, IRLen: 04, CoreSight JTAG-DP
****** Error: Cortex-A/R-JTAG (connect): Could not determine address of core debug registers. Incorrect CoreSight ROM table in device?
***************************************************
J-Link script: iMX7D Cortex-A7_0 core J-Link script
***************************************************
TotalIRLen = 4, IRPrint = 0x01
JTAG chain detection found 1 devices:
#0 Id: 0x5BA00477, IRLen: 04, CoreSight JTAG-DP
***************************************************
J-Link script: iMX7D Cortex-A7_0 core J-Link script
***************************************************
TotalIRLen = 4, IRPrint = 0x01
JTAG chain detection found 1 devices:
#0 Id: 0x5BA00477, IRLen: 04, CoreSight JTAG-DP
Cannot connect to target.
And there may be slightly more versions of the same …
Is there configuration conflict with Linux kernel preventing JTAG access to the core(s) after boot?
I observe that I have the same trouble on NXP’s SABRE board - after Linux starts I cannot connect & debug code.
On some random occasions on SABRE it seems to succeed, but then the entire chip/SoC gets reset sometime at or after trying to upload M4 code.
Anyone resolved this? A help would be appreciated in this regard.
(I’ve asked a day ago on the NXP forum too, but had no answers or suggestions of any sort yet)