Hi, I just customized my device tree by modifying imx6qdl-colibri.dtsi and imx6dl-colibri-eval-v3.dts. However, after updating, the system stuck at starting the kernel…
I disabled some nodes in original dts including lcd, uart123, weim.
Can anyone help me with this problem?
Can you share the changes you made by providing the output of
git diff
from the kernel source tree. Also provide the boot log please.
--- a/dts/imx6dl-colibri-eval-v3.dts
+++ b/dts/imx6dl-colibri-eval-v3.dts
@@ -126,7 +126,6 @@
/* Colibri SPI */
&ecspi4 {
status = "okay";
-
mcp258x0: mcp258x@1 {
compatible = "microchip,mcp2515";
reg = <0>;
@@ -143,6 +142,17 @@
status = "disabled";
};
};
+/* connect device to additional SPI bus
+&ecspi1 {
+ status = "okay";
+};
+&ecspi2 {
+ status = "okay";
+};
+&ecspi3 {
+ status = "okay";
+};
+*/
&hdmi_audio {
status = "okay";
@@ -156,6 +166,7 @@
status = "okay";
};
+
/*
* I2C: I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier
* board)
@@ -204,7 +215,8 @@
&pinctrl_weim_gpio_5 &pinctrl_weim_gpio_6
&pinctrl_csi_gpio_1
&pinctrl_gpio_1
- &pinctrl_gpio_2
+ &pinctrl_gpio_2 /*may cause conflict with can1*/
+ &pinctrl_gpio_3 /*THIS NODE IS DEFINED BY ME*/
&pinctrl_usbh_oc_1 &pinctrl_usbc_id_1>;
gpio {
@@ -214,11 +226,80 @@
MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 PAD_CTRL_HYS_PD /* SODIMM 30 */
>;
};
+ /* this node configure other pin to gpio*/
+ pinctrl_gpio_3: gpio_3 {
+ fsl,pins = <
+ MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 PAD_CTRL_HYS_PU /* conflict with weim (already disabled)*/
+ MX6QDL_PAD_SD4_DAT6__GPIO2_IO14 PAD_CTRL_HYS_PU /* conflict with uart (already disabled)*/
+ MX6QDL_PAD_SD4_DAT5__GPIO2_IO13 PAD_CTRL_HYS_PU /* conflict with uart (already disabled)*/
+ MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 PAD_CTRL_HYS_PU /* conflict with uart (already disabled)*/
+ MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 PAD_CTRL_HYS_PU /* conflict with uart (already disabled)*/
+ MX6QDL_PAD_NANDF_D7__GPIO2_IO07 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_NANDF_D6__GPIO2_IO06 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_EIM_RW__GPIO2_IO26 PAD_CTRL_HYS_PU /* conflict with weim (already disabled)*/
+ MX6QDL_PAD_EIM_OE__GPIO2_IO25 PAD_CTRL_HYS_PU /* conflict with weim (already disabled)*/
+
+ MX6QDL_PAD_EIM_DA8__GPIO3_IO08 PAD_CTRL_HYS_PU /* pins below are conflict with weim (already disabled)*/
+ MX6QDL_PAD_EIM_DA0__GPIO3_IO00 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_EIM_DA9__GPIO3_IO09 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_EIM_DA1__GPIO3_IO01 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_EIM_DA10__GPIO3_IO10 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_EIM_DA2__GPIO3_IO02 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_EIM_DA11__GPIO3_IO11 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_EIM_DA3__GPIO3_IO03 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_EIM_DA12__GPIO3_IO12 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_EIM_DA4__GPIO3_IO04 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_EIM_DA13__GPIO3_IO13 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_EIM_DA5__GPIO3_IO05 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_EIM_DA14__GPIO3_IO14 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_EIM_DA6__GPIO3_IO06 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_EIM_DA15__GPIO3_IO15 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_EIM_DA7__GPIO3_IO07 PAD_CTRL_HYS_PU /*All the pins above are conflicted with weim (disabled)*/
+ MX6QDL_PAD_EIM_EB0__GPIO2_IO28 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_EIM_D19__GPIO3_IO19 PAD_CTRL_HYS_PU /* conflict with uart (already disabled)*/
+ MX6QDL_PAD_EIM_D23__GPIO3_IO23 PAD_CTRL_HYS_PU /* conflict with uart (already disabled)*/
+
+ MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 PAD_CTRL_HYS_PU /* MX6QDL_PAD_DISP0_DAT0 -- MX6QDL_PAD_DISP0_DAT17 are conflicted with lcd(disabled) */
+ MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_DISP0_DAT8__GPIO4_IO29 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07 PAD_CTRL_HYS_PU
+
+
+ MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 PAD_CTRL_HYS_PU /* pins above are all conflicted with lcd(disabled) */
+
+ MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 PAD_CTRL_HYS_PU /* pins below are all conflicted with weim(disabled) */
+ MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_CSI0_DAT6__GPIO5_IO24 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 PAD_CTRL_HYS_PU
+
+ MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_CSI0_DAT15__GPIO6_IO01 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_CSI0_DAT16__GPIO6_IO02 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05 PAD_CTRL_HYS_PU /* pins above are all conflicted with weim */
+ MX6QDL_PAD_SD4_CMD__GPIO7_IO09 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_SD4_CLK__GPIO7_IO10 PAD_CTRL_HYS_PU /* both are conflicted with uart3(disabled) */
+
+ >;
+ };
};
};
&lcd {
- status = "okay";
+/*status = "okay";*/
+status = "disabled";
};
&mxcfb1 {
@@ -254,18 +335,21 @@
};
&uart1 {
- status = "okay";
+/*status = "okay";*/
+status = "disabled";
};
&uart2 {
- status = "okay";
+/*status = "okay";*/
+status = "disabled";
#if 0
linux,rs485-enabled-at-boot-time;
#endif
};
&uart3 {
- status = "okay";
+/*status = "okay";*/
+status = "disabled";
};
&usbh1 {
@@ -283,7 +367,9 @@
};
&weim {
- status = "okay";
+ /* disable this node to avoid pin mux conflicts */
+ /*status = "okay";*/
+ status = "disabled";
/* weim memory map: 32MB on CS0, 32MB on CS1, 32MB on CS2 */
ranges = <0 0 0x08000000 0x02000000
1 0 0x0a000000 0x02000000
(END)
I need to use a lot of GPIO, so I disabled many functions. I am not sure if this would cause failure of booting the system.
How about adhering to the base engineering principle of changing your system step-by-step?
Thanks! I’m working on it.