HI I’m working on a project, and I wondered if virtual csi can be implemented on the iMX8M Plus SODIMM module?
I noticed there is another thread with a similar question.
But this was regarding the more powerful iMX8QM.
The current plan/hope is to run 4 * HD cameras ideally at 30FPS but slightly lower is fine too… while occasionally taking 2K still snapshots. Allow some simple image processing and AI processing (passed to the AI core), and then encode the streams to h265/264 files to be stored locally, and possible streamed over network at a lower bit rate.
It would be great if we can do this on a single SBC…
To summarise:
Can the iMX8M Plus do virtual csi, to run 4 HD 2 lane cameras?
If so, would the wire up be, shared clock line, lane 1&2 camera 1, lane 3&4 = camera 2?
And can the SOC cope with all that work, or am I asking too much of it?
Can the iMX8M Plus do virtual csi, to run 4 HD 2 lane cameras?
Unfortunately, the MIPI-CSI interfaces on the i.MX8MP do not support virtual channels.
Therefore the maximum number of MIPI-CSI cameras connected to the Verdin iMX8MP is two, one for each of the MIPI-CSI interfaces.
The Apalis iMX8QM and the Colibri iMX8QXP do support MIPI-CSI virtual channels, so using 4 cameras on those should be possible. But, as stated in the thread you mentioned, we have not tested this use case.
And can the SOC cope with all that work, or am I asking too much of it?
In terms of actually being able to encode the video from four streams, the following would be expected:
Colibri iMX8QXP: Unable to encode more than one stream at a time
Apalis iMX8QM: Capable of encoding multiple streams at once, testing would be required to guarantee it would meet the requirements of 4x HD at 30 fps streams.
Verdin iMX8MP: Capable of encoding multiple streams at once, I did some testing in the past that indicates it would be able to handle 4x HD streams at 30 fps.
If so, would the wire up be, shared clock line, lane 1&2 camera 1, lane 3&4 = camera 2?
I don’t think this is how MIPI-CSI virtual channels work, it is my understanding that you would need a virtual channel aggregator, either in the form of a dedicated IC or an FPGA.
Hi Bruno, thank you for getting back to me so quickly.
Thats disappointing news, I just spent the last 2 hours making a Kicad part for the i.MX8MP
But also because we thought we found the perfect SOM in the i.MX8MP …
I guess we will have to look at the other modules, the biggest issue we need to check for is good sleep state current draws and affordability.
Also thanks for letting know that I need some kind of bridge to split the mipi csi… Thats something I didnt know about (new to working on this concept)
