BSP5 SPI1 multiple chip select

Hello,

I wanted to activate both native chip-selects (cs0,cs1) for the first SPI.
My device tree looks as following after the modification: DT

The problem is that I’m becoming the following output

root@apalis-imx8:~# ls /dev/ | grep spi
apalis-spi2-cs0
spidev0.0

instead of having two spidevs for the first SPI.

Does my device tree has something wrong?

Best regrards,
Majd

Hi @majd.m

We recently updated the Spi Driver. Could you install Bsp 5.1 and check if you still the issue?

Thanks and best regards,
Jaski

Hi @jaski.tx,

Thank you for the comment. I built the BSP 5.1 and used the mentioned device tree but still the same issue.

Best regards, Majd

Hi @majd.m,

  • There is the typo in the property fsl,espi-num-chipselects - instead of fsl,spi-num-chipselects.
    It prevents one to have 2 cs for the lpspi0 controller.

  • cs-gpios should be configured properly if one wants to use non-standard pins as csX signals. If cs-gpios has invalid gpio definitions, the corresponding spi devices are not registered at all.

  • If one wants to use standard pins as csX signals, these 2 pins should re-muxed as IMX8QM_SPI0_CS0_DMA_SPI0_CS0 and IMX8QM_SPI0_CS1_DMA_SPI0_CS1.

I suppose fixing the name of fsl,spi-num-chipselects property, converting pinmuxes IMX8QM_SPI0_CS0/CS1 to a native mode and removing away the cs-gpios property should fix your issue.

Hi @olek_s.tx,

Thank you for the response. I fixed it as you suggested, however unfortunately same result on bsp5.1 :frowning:

Current related file: https://share.toradex.com/mczppjocyr7k33p?direct

Best regards, Majd

Hi @majd.m

I see one more conflict:

pinctrl_dap1_gpios
...
IMX8QM_SPI0_CS1_LSIO_GPIO3_IO06...

You should either remove the group “pinctrl_dap1_gpios” from “iomuxc” “pinctrl-0” property or remove this particular pinmux.

After that, could you please attach the full dmesg boot log.

Hi @olek_s.tx

Thank you, and sorry that I didnt notice this conflict. I removed this pin mux. Now the SPI1 works again but still with 1 cs.

Last login: Mon Nov 16 13:57:33 UTC 2020
root@apalis-imx8:~# ls /dev/ | grep spi
apalis-spi1-cs0
apalis-spi2-cs0
spidev0.0
spidev1.0

The dmesg log file: dmesg

Thanks, @majd.m!

I see the root of the cs issue:
[ 0.473039] fsl_lpspi 5a000000.spi: cs1 >= max 1

I’m sorry to have misled you, the spi driver can’t use the native cs signals in the master mode. GPIO only.
So that there are working parts of DT for 2 spi channels on the same controller:

iomux:

                /* Apalis SPI1 */
                pinctrl_lpspi0: lpspi0grp {
                        fsl,pins = <
                                IMX8QM_SPI0_SCK_DMA_SPI0_SCK                    0x0600004c
                                IMX8QM_SPI0_SDO_DMA_SPI0_SDO                    0x0600004c
                                IMX8QM_SPI0_SDI_DMA_SPI0_SDI                    0x0600004c
                                IMX8QM_SPI0_CS0_LSIO_GPIO3_IO05                 0x0600004c
                                IMX8QM_SPI0_CS1_LSIO_GPIO3_IO06                 0x00000021
                        >;
                };

lpspi:

&lpspi0 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_lpspi0>;
        #address-cells = <1>;
        #size-cells = <0>;
        fsl,spi-num-chipselects = <2>;
        cs-gpios = <&lsio_gpio3 5 GPIO_ACTIVE_LOW>,
                   <&lsio_gpio3 6 GPIO_ACTIVE_LOW>;

        spidev0: spi@0 {
                compatible = "toradex,evalspi";
                reg = <0>;
                spi-max-frequency = <20000000>;
        };
        spidev1: spi@1 {
                compatible = "toradex,evalspi";
                reg = <1>;
                spi-max-frequency = <20000000>;
        };
};

And don’t forget to remove the group pinctrl_dap1_gpios from the &iomuxc’s pinctrl-0.

I checked it on my side - works well.

Hi @olek_s.tx,

Thanks again for the support. Actually in the BSP3.0b3 we used to use the SPI1 as master with 2 native chip selects and it was working properly. Is it an issue in the BSP5.x ?
Although the SPI1 in the BSP5.x worked sofar with 1 native cs as master without problem too.

Best regards, Majd

You’re right, just saw the wrong part of the driver :slight_smile:

So just remove cs-gpios property in the previous solution and use this variant of pin mixing:

        /* Apalis SPI1 */
        pinctrl_lpspi0: lpspi0grp {
                fsl,pins = <
                        IMX8QM_SPI0_SCK_DMA_SPI0_SCK                    0x0600004c
                        IMX8QM_SPI0_SDO_DMA_SPI0_SDO                    0x0600004c
                        IMX8QM_SPI0_SDI_DMA_SPI0_SDI                    0x0600004c
                        IMX8QM_SPI0_CS0_DMA_SPI0_CS0                    0x0600004c
                        IMX8QM_SPI0_CS1_DMA_SPI0_CS1                    0x0600004c
                >;
        };

Here what we’ve got:

lrwxrwxrwx 1 root root      9 Nov 17 18:54 /dev/apalis-spi1-cs0 -> spidev0.0
lrwxrwxrwx 1 root root      9 Nov 17 18:54 /dev/apalis-spi1-cs1 -> spidev0.1
lrwxrwxrwx 1 root root      9 Nov 17 18:54 /dev/apalis-spi2-cs0 -> spidev1.0
crw------- 1 root root 153, 0 Nov 17 18:54 /dev/spidev0.0
crw------- 1 root root 153, 1 Nov 17 18:54 /dev/spidev0.1
crw------- 1 root root 153, 2 Nov 17 18:54 /dev/spidev1.0

Hello @olek_s.tx

it worked thank you for your help. However the cs-gpios should actually be added. I tried without this property but the SPI couldnt work in the program.

So to make it work I added:

cs-gpios=<0>,<0>;

eventhough native chip select is used

Best regards, Majd

HI @majd.m

I tried without this property but the SPI couldnt work in the program.

What exactly did not work?

Hi @jaski.tx

everything works fine. I just wanted to say the property cs-gpios, should be added otherwise it won’t work.

you can mark the question as answered. Thank you

Best regards, Majd

Thanks for your valuable Input.

Best regards,
Jaski