bare metal hmp gpio access

I have the apalis evaluation board V1.1Z and apalix iMX8QM 8GB WB IT V1.1A with the hopes of developing it to replace an existing system with HMP for reading sensors and controlling motors. I understand how to reserve DRAM between the host processor and the M processors and intend to use that as a mechanism to communicate between the host program and the firmwares running on the M processors.

Are there any resources for directly accessing GPIO from a bare metal firmware running on the M processors? Is it possible to develop the firmware directly in assembly and still access the GPIO? In the system we hope to replace, it is possible to get single clock cycle access to the GPIO pins through a register while using assembly for precise timing.

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GPIO Access for Cortex-M4 Bare Metal Development

Your Apalis iMX8QM module includes dual Cortex-M4F cores running at 266 MHz (1), which are ideal for hard real-time applications requiring precise timing control (2). The heterogeneous multicore architecture allows offloading critical real-time tasks to these Cortex-M4 processors for extremely low latency (3).

Hardware Capabilities

The Apalis iMX8QM provides extensive GPIO capabilities with up to 133 GPIO pins available (1). The Cortex-M4F cores feature:

  • Clock Speed: 266 MHz (1)
  • Tightly-Coupled Memory (TCM): 256 KB (1)
  • Cache Configuration: 16 KB L1 instruction cache, 16 KB L1 data cache (1)
  • Floating Point Unit: Yes (1)

Development Resources

Toradex provides tooling and FreeRTOS to simplify development on the Cortex-M4 cores (3). The company invests in making the M4 core easily accessible, including Visual Studio Code integration (2).

Assembly Development and Direct Register Access

Yes, it is possible to develop firmware directly in assembly for the Cortex-M4 cores. The GPIO peripheral on the i.MX8QM supports direct register access, which can provide the single clock cycle access you need for precise timing applications.

The GPIO modules feature:

  • Set/clear functionality: Firmware writes 1 to corresponding bit positions to set or clear GPIO signals without requiring critical section protection [^FAQ]
  • Separate Input/Output registers: Output registers reflect drive status, while input registers reflect pin status [^FAQ]
  • Direct register access: GPIO output signals can be toggled by direct write to output registers [^FAQ]

Memory Architecture Benefits

Your approach of using reserved DRAM for communication between the host processor and M4 cores is well-suited for this platform. The Cortex-M4 cores have access to both their tightly-coupled memory (256 KB TCM) (1) and shared system memory, enabling efficient data exchange while maintaining real-time performance.

Application Suitability

The Apalis iMX8QM is specifically designed for applications requiring hard real-time capabilities (3). The Cortex-M4 cores can handle microsecond-level latencies, making them suitable for precise motor control and sensor reading applications where timing is critical.

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Please refer to the following documentation for details related to Heterogeneous Multicore Processing (HMP) on Toradex modules:
https://developer.toradex.com/software/cortex-m/

C examples demonstrating access to GPIO and other peripherals are included in the MCUXpresso SDK.

Alexander Samutin
Toradex