Hi @farina
The Documentation of the SoC iMX7 is very generic. For the correct speed calculation of Spi Transfer, one needs to consult the section 4.11.1.1 of the datasheet, which describes the SCLK Cycle. The read timing for the master mode is 43 ns, which results in 23 Mbit/s for maximum frequency of SCLK.
Please have a look here too.
Best regards,
Jaski