Hi,
I am in the process of working on the PCBA layout for a SoM carrier board using the Apalis iMX8QM 8GB WB IT V1.1A (00671100).
We are adding an Ethernet PHY to this board, to allow us to use Ethernet 2 from this SOM.
Could you please provide the propagation delays (from the iMX8) within the SoM for the RGMII data and clock lines for Ethernet 2?
I need this data so we can adequately delay match these signals on the carrier board.
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Hello,
Thank you for your question regarding the propagation delays for the RGMII data and clock signals for Ethernet 2 on the Apalis iMX8QM SoM.
Unfortunately, the specific propagation delays within the SoM for these RGMII signals are not explicitly stated in the available documentation. The Apalis iMX8 features a second Ethernet port, and the second MAC of the SoC provides RGMII for connecting a Gigabit Ethernet PHY on the carrier board. However, precise intra-SoM signal delay figures are not published.
For best practice, it is generally recommended to match the lengths of the RGMII data and clock lines from the SoM connector to the external PHY as closely as possible on your carrier board layout. This helps ensure timing integrity, as the longest unmatched trace (not the internal SoM routing) is usually the limiting factor. Refer to the PHY vendor’s recommendations for maximum allowable skew and be aware that most designs target a difference of less than 50 mils (~1.25 mm) with tighter matching for the clock line, if possible.
For further general guidance on Ethernet 2 configuration and RGMII PHY design with Apalis iMX8, you may find the following documentation helpful:
If you need additional information regarding recommended carrier board trace layout techniques or best practices for RGMII, feel free to ask!
Best regards,
Toradex AI Assistant.
Hi,
While these numbers aren’t published, is this something that someone from the technical team can please find in the design files of the SoM and provide here?
RXC and TXD3 are a fair distance from the rest of their signals, so I would like to confirm if they are still delay matched within the SOM.
Hi @matthew.walker.pi , yes, all RGMII signals are equally routed from SoC to the edge connector.
