Apalis iMX6Q PCIe

Technical Support
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1

Hi all,

I am using the iMX6Q Apalis and would like to make PCIe working on a custom board with an Artix-7 as a PCIe endpoint. However, on every boot, I’m greated with the following messages:

[    0.321358] imx6q-pcie 1ffc000.pcie: 1ffc000.pcie supply epdev_on not found, using dummy regulator
[    0.609430] imx6q-pcie 1ffc000.pcie: host bridge /soc/pcie@1ffc000 ranges:
[    0.609442] imx6q-pcie 1ffc000.pcie: Parsing ranges property...
[    0.609474] imx6q-pcie 1ffc000.pcie:    IO 0x01f80000..0x01f8ffff -> 0x00000000
[    0.609494] imx6q-pcie 1ffc000.pcie:   MEM 0x01000000..0x01efffff -> 0x01000000
[    1.603017] imx6q-pcie 1ffc000.pcie: Phy link never came up
[    1.614673] imx6q-pcie 1ffc000.pcie: failed to initialize host
[    1.622486] imx6q-pcie 1ffc000.pcie: unable to add pcie port.

The Artix-7 design used in this case is the following:

2653-artix7-pcie-test-design.png
2653-artix7-pcie-test-design.png1469×685 64.8 KB

The problem here seems to be with the REFCLK_0 signal (which is the interface to the PCI clock). Indeed, its value is always 1. Thus, the mmcm_lock signal has always the value 0, indicating that the reference clock is not stable.

Moreover, I disabled the PCIe switch driven by I2C in the Device Tree since there is no such switch on the custom board - pcie-switch@58 entry in imx6q-apalis-eval.dts.

I can’t figure out what I’m doing wrong.

The only thing that seems odd to me is that I did not add an entry about the AXI Memory Mapped To PCI Express IP in the device tree but I don’t think this is mandatory. To be fair, I tried but everytime the driver fails saying it could not register irq 0.

Does someone have a clue about what is going on here? I’m completely out of ideas.

Thank you very much in advance.

Lucas

EDIT: I don’t know if it helps but I can’t even execute devmem 0x01FFC000 32. The commands hangs and the device becomes non-responsive.

2

Dear @lei-reds,

The PCIe clock will only be active for a short period of time ~100ms except the LTSSM (Link Training and Status State Machine) finished with success. There is a very good paper provided about troubleshooting PCIe links.

PCIe Troubleshooting

From the output you sent you can see that link-training fails. Usually this points to either a HW design issue or some flaw in the FPGA design. Another option is that the bitstream is loaded to late.

I would recommend you follow the troubleshooting guide, this will give you further insight on what point in time your link fails.

Best Regards
Kevin

3

After discussing and debugging the design and the custom board with the hardware engineers, we found out that there was a missing capacitor on the PCIe reference clock line between the Apalis iMX6Q and the board.

However, the hardware engineers told me that this capacitor was marked as not needed in the Toradex’s Carrier Board Design Guide v1.9 (p. 18).
In fact, after some research, we found out conflicting information:

  • page 14: Special care needs to be taken to determine as to whether or not AC coupling capacitors are required.
  • page 18: The reference clock lines do not need decoupling capacitors.

@kevin.tx I feel like one of the two notes should be removed from the document to avoid future confusion.
Anyway, thanks for your answer.

I hope this answer will be helpful to others!

Lucas

4

Dear @lei-reds,

I am glad that you found the source of the issue.

Thank you for pointing out the conflicting information, we are looking into it and we will change it in a way that there won’t be any confusion about this.

Best Regards
Kevin