APALIS IMX6q on ixora with LVDS 1920x1200 dual channel in split-mode

I have an Apalis IMX6q, on an Ixora carier and want to attach an LVDS display 1920x1200 that use 2 channels LVDS.

I configured DTS in this way:

diff --git a/arch/arm/boot/dts/imx6qdl-apalis.dtsi b/arch/arm/boot/dts/imx6qdl-apalis.dtsi
index cebd78f2a34e..78b8c3bc83c2 100644
--- a/arch/arm/boot/dts/imx6qdl-apalis.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-apalis.dtsi
@@ -92,10 +92,10 @@
        mxcfb1: fb@0 {
                compatible = "fsl,mxc_sdc_fb";
                disp_dev = "ldb";
-               interface_pix_fmt = "RGB666";
-               default_bpp = <16>;
+               interface_pix_fmt = "LVDS666";
+               default_bpp = <32>;
                int_clk = <0>;
                status = "disabled";
        };
 
@@ -523,19 +523,34 @@
 &ldb {
        status = "okay";
-//     split-mode;
+       split-mode;
 //     dual-mode;
 
        lvds-channel@0 {
                reg = <0>;
                fsl,data-mapping = "spwg"; /* "jeida"; */
-               fsl,data-width = <18>;
+               fsl,data-width = <24>;
                crtc = "ipu2-di1";
                primary;
                status = "okay";
 
                display-timings {
-                       native-mode = <&timing_xga>;
+                       native-mode = <&timing_wuxga>;
+                       timing_wuxga: 1920x1200M {
+                               clock-frequency = <149992500>;
+                               hactive = <1920>;
+                               hback-porch = <20>;
+                               hfront-porch = <100>;
+                               hsync-len = <18>;
+                               hsync-active = <0>;
+                               vactive = <1200>;
+                               vback-porch = <4>;
+                               vfront-porch = <6>;
+                               vsync-len = <2>;
+                               vsync-active = <0>;
+                               de-active = <1>;
+                               pixelclk-active = <0>;
+                       };
                        /* LDB-AM-800600LTNQW-A0H */
                        timing_svga: 800x600 {
                                clock-frequency = <55000000>;

And if I start the kernel with:

setenv vidargs 'video=mxcfb1:off video=mxcfb2:off video=mxcfb3:off fbmem=32M'

I get bad image:

[upload|gfL8fa19pZxIDsb0JXA85eE+JV8=]

But the time parameters are configured correctly:

[   24.102946] mxc_sdc_fb fb@0: 1920x1200 h_sync,r,l: 18,100,20  v_sync,l,u: 2,6,4 pixclock=149992000 Hz
root@apalis-imx6:~# [   24.301451] mxc_sdc_fb fb@0: 1920x1200 h_sync,r,l: 18,100,20  v_sync,l,u: 2,6,4 pixclock=149992000 Hz
[   24.399321] mxc_sdc_fb fb@0: 1920x1200 h_sync,r,l: 18,100,20  v_sync,l,u: 2,6,4 pixclock=149992000 Hz
[   24.499760] mxc_sdc_fb fb@0: 1920x1200 h_sync,r,l: 18,100,20  v_sync,l,u: 2,6,4 pixclock=149992000 Hz

root@apalis-imx6:~# [   31.827127] mxc_sdc_fb fb@0: 1920x1200 h_sync,r,l: 18,100,20  v_sync,l,u: 2,6,4 pixclock=149992000 Hz

root@apalis-imx6:~# 
root@apalis-imx6:~# [   36.313123] usb_otg_vbus: disabling
fbset

mode "1920x1200-60"
    # D: 149.993 MHz, H: 72.883 kHz, V: 60.134 Hz
    geometry 1920 1200 1920 1200 32
    timings 6667 20 100 4 6 18 2
    rgba 8/16,8/8,8/0,8/24
endmode

Noting that the right side seems stretched, like the secondary channel is not configured or configured with a bad parameters

Now if I start the kernel with this parameters

setenv vidargs 'video=mxcfb0:dev=ldb,1920x1200M@60,if=LVDS666 video=mxcfb1:off video=mxcfb2:off video=mxcfb3:off fbmem=32M'

It will seems better (there are some flickerig and bad timing parameters configured, the clock is very high 194Mhz (why?!?!))

[upload|+MDKBXGOiep+Lns86XOP9qaMNsU=]

[   13.098593] mxc_sdc_fb fb@0: 1920x1200 h_sync,r,l: 200,136,336  v_sync,l,u: 6,3,36 pixclock=193274000 Hz
[   13.289203] mxc_sdc_fb fb@0: 1920x1200 h_sync,r,l: 200,136,336  v_sync,l,u: 6,3,36 pixclock=193274000 Hz
[   13.366268] mxc_sdc_fb fb@0: 1920x1200 h_sync,r,l: 200,136,336  v_sync,l,u: 6,3,36 pixclock=193274000 Hz
[   13.436650] mxc_sdc_fb fb@0: 1920x1200 h_sync,r,l: 200,136,336  v_sync,l,u: 6,3,36 pixclock=193274000 Hz
[   13.448381] IPv6: ADDRCONF(NETDEV_UP): usb0: link is not ready
[   14.042231] mxc_sdc_fb fb@0: 1920x1200 h_sync,r,l: 200,lock=193274000 Hz
[   36.313195] usb_otg_vbus: disabling
root@apalis-imx6:~#                 
root@apalis-imx6:~# 
root@apalis-imx6:~# fbset

mode "1920x1200-60"
    # D: 193.274 MHz, H: 74.566 kHz, V: 59.892 Hz
    geometry 1920 1200 1920 1200 32
    timings 5174 336 136 36 3 200 6
    vsync high
    rgba 8/16,8/8,8/0,8/24

The parameters are not what I configured in DTS, and if I set them with fbset

root@apalis-imx6:~# fbset -t 6667 20 100 4 6 18 2 -vsync false -g 1920 1200 1920 1200 32 -s
[  225.206666] mxc_sdc_fb fb@0: 1920x1200 h_sync,r,l: 18,100,20  v_sync,l,u: 2,6,4 pixclock=149992000 Hz

mode "1920x1200-60"
    # D: 149.993 MHz, H: 72.883 kHz, V: 60.134 Hz
    geometry 1920 1200 1920 1200 32
    timings 6667 20 100 4 6 18 2
    rgba 8/16,8/8,8/0,8/24
endmode

Now everything seems better, the timing and image seems very good:

[upload|0Tfk1PkdHzn79JZNZufMz0Taugs=]

Now:

  1. What’s the difference from video:dev=ldb,1920x1200M,if=LVDS666 and my DTS mxcfb1: fb@0 configuration? I suppose that the if=LVDS666 is not the same as interface_pix_fmt = “LVDS666”;
    in my DTS!?
  2. The M in mode 1920x1200M will do some automatic calculation of timing, but it is wrong, but probably do some other thing that my DTS not configure
  3. How I can setting all in the DTS?
  4. … Or how I can sett all parameters (timing and pixel clock and vsync=false) in the vidargs at startup?

HI @kyakan and Welcome to the Toradex Community!

What’s the difference from video:dev=ldb,1920x1200M,if=LVDS666 and my DTS mxcfb1: fb@0 configuration? I suppose that the if=LVDS666 is not the same as interface_pix_fmt = “LVDS666”; in my DTS!?

Why do you think, there is a difference between these?

The M in mode 1920x1200M will do some automatic calculation of timing, but it is wrong, but probably do some other thing that my DTS not configure

Usually this should work, maybe some wrong clock dividers were used. Could you share the clock summary: cat /sys/kernel/debug/clk/clk_summary

How I can setting all in the DTS?

As you have done. Could you share a datasheet of your display?

Or how I can sett all parameters (timing and pixel clock and vsync=false) in the vidargs at startup?

We recommend you to use parameters in devicetree.

Additionally for getting the pixel clock frequency closer to the desired value, you might have to choose a different parent clock as discussed here.

Best regards,
Jaski

Thanks for reply @jaski.tx

current DTS patch is this

diff --git a/arch/arm/boot/dts/imx6qdl-apalis.dtsi b/arch/arm/boot/dts/imx6qdl-apalis.dtsi
index cebd78f2a34e..a93f429a922f 100644
--- a/arch/arm/boot/dts/imx6qdl-apalis.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-apalis.dtsi
@@ -92,8 +92,9 @@
        mxcfb1: fb@0 {
                compatible = "fsl,mxc_sdc_fb";
                disp_dev = "ldb";
-               interface_pix_fmt = "RGB666";
-               default_bpp = <16>;
+               interface_pix_fmt = "LVDS666";
+               mode_str ="1920x1200M@60";
+               default_bpp = <32>;
                int_clk = <0>;
                late_init = <0>;
                status = "disabled";
@@ -101,10 +102,10 @@
 
        mxcfb2: fb@1 {
                compatible = "fsl,mxc_sdc_fb";
-               disp_dev = "hdmi";
-               interface_pix_fmt = "RGB24";
-               mode_str ="1920x1080M@60";
-               default_bpp = <16>;
+               disp_dev = "ldb";
+               interface_pix_fmt = "LVDS666";
+               mode_str ="1920x1200M@60";
+               default_bpp = <32>;
                int_clk = <0>;
                late_init = <0>;
                status = "disabled";
@@ -523,19 +524,34 @@
 
 &ldb {
        status = "okay";
-//     split-mode;
+       split-mode;
 //     dual-mode;
 
        lvds-channel@0 {
                reg = <0>;
                fsl,data-mapping = "spwg"; /* "jeida"; */
-               fsl,data-width = <18>;
+               fsl,data-width = <24>;
                crtc = "ipu2-di1";
                primary;
                status = "okay";
 
                display-timings {
-                       native-mode = <&timing_xga>;
+                       native-mode = <&timing_wuxga>;
+                       timing_wuxga: 1920x1200 {
+                               clock-frequency = <149992500>;
+                               hactive = <1920>;
+                               hback-porch = <20>;
+                               hfront-porch = <100>;
+                               hsync-len = <18>;
+                               hsync-active = <0>;
+                               vactive = <1200>;
+                               vback-porch = <4>;
+                               vfront-porch = <6>;
+                               vsync-len = <2>;
+                               vsync-active = <0>;
+                               de-active = <1>;
+                               pixelclk-active = <0>;
+                       };
                        /* LDB-AM-800600LTNQW-A0H */
                        timing_svga: 800x600 {
                                clock-frequency = <55000000>;

And if I start the kernel with this vidargs:

vidargs=video=mxcfb1:off video=mxcfb2:off video=mxcfb3:off fbmem=32M

I will get this resolution selected:

root@apalis-imx6:~# xrandr --verbose
Screen 0: minimum 240 x 240, current 1920 x 1200, maximum 8192 x 8192
DISP4 BG - DI1 connected primary 1920x1200+0+0 (0x40) normal (normal left inverted right x axis y axis) 0mm x 0mm
        Identifier: 0x3f
        Timestamp:  11325
        Subpixel:   unknown
        Gamma:      1.0:1.0:1.0
        Brightness: 1.0
        Clones:    
        CRTC:       0
        CRTCs:      0
        Transform:  1.000000 0.000000 0.000000
                    0.000000 1.000000 0.000000
                    0.000000 0.000000 1.000000
                   filter: 
        non-desktop: 0 
                supported: 0, 1
  U:1920x1200p-59 (0x40) 193.274MHz -HSync +VSync -CSync *current +preferred             <--------- pixel clock @ 194MHz !!!
        h: width  1920 start 2056 end 2256 total 2592 skew    0 clock  74.57KHz      <--- with h-porch not taken from my dts
        v: height 1200 start 1203 end 1209 total 1245           clock  59.89Hz    <-------- as the vporch, not as my dts
  U:1920x1200p-60 (0x41) 149.992MHz -HSync -VSync -CSync     <--- This is my (right) configuration!
        h: width  1920 start 2020 end 2038 total 2058 skew    0 clock  72.88KHz    <---right hporch
        v: height 1200 start 1206 end 1208 total 1212           clock  60.13Hz          <--- right vporch
  U:1920x1080p-59 (0x42) 138.504MHz -HSync -VSync -CSync
        h: width  1920 start 1968 end 2000 total 2080 skew    0 clock  66.59KHz
        v: height 1080 start 1083 end 1088 total 1111           clock  59.94Hz
  U:1280x800p-59 (0xnc
        h: width  1280 start 1340 end 1380 total 1440 skew    0 clock  49.38KHz
        v: height  800 start  807 end  816 total  823           clock  60.00Hz
  U:1280x800p-58 (0x44) 68.932MHz -HSync -VSync -CSync
        h: width  1280 start 1344 end 1384 total 1448 skew    0 clock  47.60KHz
        v: height  800 start  805 end  811 total  816           clock  58.34Hz
  U:1024x768p-60 (0x45) 65.002MHz -HSync -VSync -CSync
        h: width  1024 start 1048 end 1184 total 1344 skew   24 clock  48.36KHz
        v: height  768 start  771 end  777 total  806           clock  60.01Hz
  U:800x600p-86 (0x46) 55.002MHz -HSync -VSync -CSync
        h: width   800 start  832 end  912 total 1024 skew    0 clock  53.71KHz
        v: height  600 start  617 end  621 total  624           clock  86.08Hz

Now with my timing (U:1920x1200p-60 (0x41) …) i get a good result, but with the default I get something like the image bad-timing.jpg , a good resolution but with bad timing parameters, and the clock summary attached in Log Clock with 1920x1200M resolution

Now if I change the vidargs with this:

vidargs=video=mxcfb0:dev=ldb,1920x1200@60,if=LVDS666 video=mxcfb1:off video=mxcfb2:off video=mxcfb3:off fbmem=32M

root@apalis-imx6:~# xrandr --verbose
Screen 0: minimum 240 x 240, current 1920 x 1200, maximum 8192 x 8192
DISP4 BG - DI1 connected primary 1920x1200+0+0 (0x40) normal (normal left inverted right x axis y axis) 0mm x 0mm
        Identifier: 0x3f
        Timestamp:  11614
        Subpixel:   unknown
        Gamma:      1.0:1.0:1.0
        Brightness: 1.0
        Clones:    
        CRTC:       0
        CRTCs:      0
        Transform:  1.000000 0.000000 0.000000
                    0.000000 1.000000 0.000000
                    0.000000 0.000000 1.000000
                   filter: 
        non-desktop: 0 
                supported: 0, 1
  U:1920x1200p-60 (0x40) 149.992MHz -HSync -VSync -CSync *current +preferred    <--- Correct pixel clock and h/v-porch as in the DTS
        h: width  1920 start 2020 end 2038 total 2058 skew    0 clock  72.88KHz
        v: height 1200 start 1206 end 1208 total 1212           clock  60.13Hz
  U:1920x1080p-59 (0x41) 138.504MHz -HSync -VSync -CSync
        h: width  1920 start 1968 end 2000 total 2080 skew    0 clock  66.59KHz
        v: height 1080 start 1083 end 1088 total 1111           clock  59.94Hz
  U:1280x800p-59 (0x42) 71.103MHz -HSync -VSync -CSync
        h: width  1280 start 1340 end 1380 total 1440 skew    0 clock  49.38KHz
        v: height  800 start  807 end  816 total  823           clock  60.00Hz
  U:1280x800p-58 (0x43) 68.932MHz -HSync -VSync -CSync
        h: width  1280 start 1344 end 1384 total 1448 skew    0 clock  47.60KHz
        v: height  800 start  805 end  811 total  816           clock  58.34Hz
  U:1024x768p-60 (0x44) 65.002MHz -HSync -VSync -CSync
        h: width  1024 start 1048 end 1184 total 1344 skew    0 clock  48.36KHz
        v: height  768 start  771 end  777 total  806           clock  60.01Hz
  U:800x600p-86 (0x45) 55.002MHz -HSync -VSync -CSync
        h: width   800 start  832 end  912 total 1024 skew    0 clock  53.71KHz
        v: height  600 start  617 end  621 total  624           clock  86.08Hz

But I get a bad image, it is streched in the right side, as in the image bad-resolutio-color-console.jpg, and with the clock summary like this Clock with 1920x1200 without M

Display as this timing and summary

About choosing the right parent clock, the timing that I found with 1920x1200M are exactly the same calculated with

$ gtf 1920 1200 60
  # 1920x1200 @ 60.00 Hz (GTF) hsync: 74.52 kHz; pclk: 193.16 MHz
  Modeline "1920x1200_60.00"  193.16  1920 2048 2256 2592  1200 1201 1204 1242  -HSync +Vsync

But are wrong for my case, seems that this calculate H/Bporch like with 30% of size, and calculate the pixel clock respect to this, if I give another resolution I get rigth pixel clock, just a calculation of number of pixel with h/vporch

root@apalis-imx6:~# gtf 1640 1050 60

  # 1640x1050 @ 60.00 Hz (GTF) hsync: 65.22 kHz; pclk: 143.48 MHz
  Modeline "1640x1050_60.00"  143.48  1640 1744 1920 2200  1050 1051 1054 1087  -HSync +Vsync

So probably I must setup the resolution with 1920x1200 without M, but I need to specify the clock to get the right resolution (without streched image on the right)

HI @kyakan

Thanks for your devicetree files and all the information.

So first of all, I think your display is not supporting a resolution higher than 150MHz. Thats why choosing a frequency clock with 149 works for you.

For the CVT Calculation, usually the regular mode is used which results in a very high pixel clock frequency. The reason behind this calculation may be the description in Chapter 6.4 of this article. Nevertheless you need to use reduced blanking mode, which will lower the clock frequency and you should get a better image.

If you define your display in device-tree then the pixel clock seems to be set correctly. For the stretching problem, you can try to change the value of hsync, hfront-porch and hback-porch (same for vsync, vfront-porch and vback-porch) until you get a better image. Just the sum of these values should be the same as the value of blanking.

Best regards,
Jaski

Thaks @jaski.tx ,

So first of all, I think your display is not supporting a resolution higher than 150MHz. Thats why choosing a frequency clock with 149 works for you.

Yes I set the parameter for matching a clock under 150MHz as specified in the Display Datasheet

For the CVT Calculation, usually the regular mode is used which results in a very high pixel clock frequency. The reason behind this calculation may be the description in Chapter 6.4 of this article. Nevertheless you need to use reduced blanking mode, which will lower the clock frequency and you should get a better image.

Yes, but I doesen’t have any control on this “auto calculation”

If you define your display in device-tree then the pixel clock seems to be set correctly.

Yes it match the DS

For the stretching problem, you can try to change the value of hsync, hfront-porch and hback-porch (same for vsync, vfront-porch and vback-porch) until you get a better image. Just the sum of these values should be the same as the value of blanking.

But the image is perfect using the DTS parameter, but I need to start the system using the high clock, probably you spotted the problem when you talk about the clock, probably this mode enable/configure in the right way some clock

If I start it with resolution 1920x1200M then it start using high clock, high blank, etc but after start I simply apply my DTS configuration and it works good.

When I use my resolution directly, it doesn’t work

This two are the clock logs:

194MHz > https://share.toradex.com/nbi70fegns9v0rb?direct

149MHz > https://share.toradex.com/hauqnru7wx52gki?direct

HI @kyakan

Yes, but I doesen’t have any control on this “auto calculation”

You can use the command cvt 1920 1200 60 -r. Anyway you should define the parameters in the device-tree.

But the image is perfect using the DTS parameter, but I need to start the system using the high clock, probably you spotted the problem when you talk about the clock, probably this mode enable/configure in the right way some clock

I don’t understand what is the issue, if the image is perfect.

If I start it with resolution 1920x1200M then it start using high clock, high blank, etc but after start I simply apply my DTS configuration and it works good.

When I use my resolution directly, it doesn’t work

Why do you need to define the resolution with vidargs if it works with devicetree files?

Best regards,
Jaski

Sorry for my bad explanation,
when it start with my DTS parameters I get the stretched image (but clock, h/v sync are good):

if I start it with 1920x1200M it start with an high clock, I get bad image during boot (high clock, bad v/h synch):

Only after boot changing resolution it is perfect but during boot I have an High clock, with bad console resolution.

Thanks for your help

HI

Sorry for my bad explanation, when it start with my DTS parameters I get the stretched image (but clock, h/v sync are good):

No problem. Regarding the stretching, you should start with setting values for hfront-porch, backporch and hsync to 1/3 of blanking value, thus the sum of these gives you the blanking’s value. And then try other values till the stretched image is no more there.

Best regards,
Jaski