Could you please give some additional information regarding #RESET_MOCI signal?
(26 RESET_MOCI# O CMOS 3.3V Active low reset output)
Is it connected to Apalis PMIC? Is it just a GPIO? There is a logic gate between the two? It is meant to be used only for PCI express or generally for carrier board peripheral reset?
In our carrier board we are using it for peripheral reset (no PCI-E), but we had some issues since gpio1 28 is required to be moved at power up, but this is not going to happen unless you add into dts:
Please refer to the latest datasheet of the Apalis iMX6. We recently added a block diagram on how RESET_MOCI# is generated.
The signal is meant for general carrier board reset, among them also PCIe.
The PCIe circuit on the Apalis Evaluation Board requires a reset sequence which first de-asserts the reset to the PCIe switch and then the REST_MOCI# which is connected to the PCIe endpoints.
This is done in the PCIe driver.
If you don’t configure the PCIe driver in the Kernel or you set PCIe to disabled in the device tree the following code takes over responsibility to de-assert RESET_MOCI. As you state correctly the reset-ep-gpio property in the pcie node is still needed.
If the special reset sequence from PCIe is not needed for a given design one could also de-assert RESET_MOCI# in U-Boot.
