Apalis iMX6 recovery mode after normal reset

My question is, if a power-on reset and a reset generated by RESET_MICO# have the same behaviour.

The datasheet of Apalis imx6 states in chapter 6:

In order to enter recovery mode, the recovery mode pads need to be shorted during the initial power-on (cold boot) of the module. It is also possible to enter the recovery mode by pulling up pin 63 of the module edge connector (TS_1) with a 1kΩ resistor while booting.

and in chapter 5.1.3:

RESET_MICO# - Reset Input: This pin is low active and resets the Apalis module. This pin is connected to the power manger IC.

On the article Flashing Embedded Linux to iMX6 Modules another phrase is used:

Apply power or reset

I would not like to have a full power cycle to get in the recovery mode. But I cannot figure out, how the RESET_MICO# is connected to the PMIC (since it doesn’t have a reset input).
Could you clearify, if a RESET_MICO# generates the same reset as a power-on will do? And that I always can enter the recovery mode?

Hi @torf_munich,

Even though it is written in our datasheet that a full power cycle is required, the recovery mode can also be entered by just pressing the reset button (pulling down RESET_MICO#). A software initiated reset on the other hand does not work.

The statement that the RESET_MICO# is connected to the power manager IC is indeed a little bit misleading. The PMIC has a reset output which is an open drain signal. There is a small circuit on the RESET_MICO# signal wich pulls down this reset output of the PMIC when the RESET_MICO# is going down. This means the RESET_MICO# is indirectly connected to the reset output of the PMIC. This means the RESET_MICO# generates the same reset signal on the internal CPU reset as a power cycle would do. The difference is that the RESET_MICO# does not do a power cycle. Therefore, some IC wich do not have an reset input and only rely on internal power-on-reset (such as the audio codec), they will not get reset by the RESET_MICO#, they will only get reset by a proper power cycle.