I assume you already checked that the backlight is on.
There are two LVDS channels on the connector. The display data is output on LVDS1_A and not LVDS1_B.
I assume that you checked that you connected to the correct channel.
- Pixel Clock
The lvds circuitry needs a clock 7 times the pixel clock. Currently its parent is set to a fixed clock of 528MHz. The system chooses a pixel clock of 37.7MHz which is below what your display expects.
Since you don’t use a second display I would assign PLL5 as the clock parent. E.g. I would extend the clk node as follows:
diff --git a/arch/arm/boot/dts/imx6qdl-apalis.dtsi b/arch/arm/boot/dts/imx6qdl-apalis.dtsi
index 73b8ee41625f4..8c985bbd59d58 100644
@@ -259,6 +259,13 @@
status = "disabled";
+ assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
+ <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
+ assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
+ <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>;
/* Apalis SPI1 */
fsl,spi-num-chipselects = <1>;
You anyway have to change the device tree. I would put the display timings also there and stop specifying them on the kernel command line. E.g. add the timings here and set the property native_mode to point to your new timings. Then vidargs would be shortened to:
video=mxcfb0:dev=ldb,if=RGB24 video=mxcfb1:off video=mxcfb2:off video=mxcfb3:off fbmem=32M
The if=RGB24 in vidargs request 24bit output from the display controller, in addition to this you have to configure the lvds converter (LDB) in the device tree.
@@ -516,7 +523,7 @@
reg = <0>;
fsl,data-mapping = “spwg”; /* “jeida”; */