Apalis iMX6 LVDS Output on IXORA Carrier Board

Technical Support
, , , ,
1

I have been using my new Ixora board with Apalis iMX6 Quad 2GB with success and I tried connecting my LCD panel to Ixora using the LVDS pins available on the board.

I followed the guide at Display Output, Resolution and Timings (Linux) | Toradex Developer Center

I have used the following boot variable but to no avail:

setenv vidargs ‘video=mxcfb0:dev=ldb,1280x480M@60,if=RGB24 ldb=sin0 video=mxcfb1:off video=mxcfb2:off video=mxcfb3:off fbmem=32M’

Am I missing something here?

Is there anything I have to set to get the output on the LCD?

I appreciate your responses.

Matteo

2

The screen flickers during boot than become black and remains this color.

3

Hi @matteo_s

Could you provide the dmesg log in a text file?
Additionally could you share the datasheet of the LCD you are using?

What is the output of fbset?

Best regards,
Jaski

4

Attached what you have requested. In log there are the dmesg log and fbset output. The other file is the datasheet of the display.

log

Display datasheet

5

Hi

  1. Backlight

I assume you already checked that the backlight is on.

  1. Connection

There are two LVDS channels on the connector. The display data is output on LVDS1_A and not LVDS1_B.
I assume that you checked that you connected to the correct channel.

  1. Pixel Clock

The lvds circuitry needs a clock 7 times the pixel clock. Currently its parent is set to a fixed clock of 528MHz. The system chooses a pixel clock of 37.7MHz which is below what your display expects.

Since you don’t use a second display I would assign PLL5 as the clock parent. E.g. I would extend the clk node as follows:

diff --git a/arch/arm/boot/dts/imx6qdl-apalis.dtsi b/arch/arm/boot/dts/imx6qdl-apalis.dtsi
index 73b8ee41625f4..8c985bbd59d58 100644
--- a/arch/arm/boot/dts/imx6qdl-apalis.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-apalis.dtsi
@@ -259,6 +259,13 @@
        status = "disabled";
 };
 
+&clks {
+        assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
+                          <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
+        assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
+                                 <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>;
+};
+
 /* Apalis SPI1 */
 &ecspi1 {
        fsl,spi-num-chipselects = <1>;
  1. Timings

You anyway have to change the device tree. I would put the display timings also there and stop specifying them on the kernel command line. E.g. add the timings here and set the property native_mode to point to your new timings. Then vidargs would be shortened to:

video=mxcfb0:dev=ldb,if=RGB24 video=mxcfb1:off video=mxcfb2:off video=mxcfb3:off fbmem=32M

  1. The if=RGB24 in vidargs request 24bit output from the display controller, in addition to this you have to configure the lvds converter (LDB) in the device tree.

    @@ -516,7 +523,7 @@
    lvds-channel@0 {
    reg = <0>;
    fsl,data-mapping = “spwg”; /* “jeida”; */

    •           fsl,data-width = <18>;

    •           fsl,data-width = <24>;
          crtc = "ipu2-di1";
          primary;
          status = "okay";

Max

6

this is a video of the flickering:video

7

Thats with all the tips and hints in my post applied?

8

No. I haven’t implemented them yet.

9

I’ve implemented the modifications you suggested on a Buildroot new OS but the clock doesn’t change is always 37MHz and the display flickers. Using an HDMI-lvds converter I got an lvds clk frequency of 47MHz.

What can I do to tell to driver to improve the frequency?

10

I’ve implemented the modifications you suggested on a Buildroot new OS but the clock doesn’t change is always 37MHz and the display flickers.

I would have started to use a regular Bsp with the changes provided by @max.tx.

Using an HDMI-lvds converter I got an lvds clk frequency of 47MHz.

Is the flickering gone?

Could you provide the dmesg log and output of fbset for the new OS with customized device-tree?

Best regards,
Jaski

11

log

12

Attached the log that you require of dmesg and fbset.

Kind regards,

Matteo

13

Now the pixel clock frequency seems to be in the specifications of the display. Is the screen still flickering?
If yes, can you make a video of this.

Best regards,
Jaski

14

The real clock is still remaining to 37MHz.

Now I can’t send you the video flickering.

Furthermore the signals LVDS TX3 is inactive.

This happens both using the Boot2Qt image or the Buildroot custom image with modified dtsi.

Kind regards,

Matteo

15

Hi @matteo_s

Did you measure the clock? The fbset gives this output:

# D: 47.751 MHz, H: 29.844 kHz, V: 59.689 Hz

This happens both using the Boot2Qt image or the Buildroot custom image with modified dtsi.

As I already said, it would be easier to integrate the changes in a regular Bsp.

Best regards,
Jaski

16

I measured the clock. It happens both… with buildroot or boot2qt.

17

Thanks for your Input. Could you explain, what changes did you make to the sources of the Boot2Qt image?