Apalis IMX6 LVDS Display Issue (Clock, ...)

I have an IMX6 board with an LVDS display attached (split-mode).

I configured the mxcfb in this way:

 mxcfb1: fb@0 {
     compatible = "fsl,mxc_sdc_fb";
     disp_dev = "ldb";
     interface_pix_fmt = "RGB24";
     mode_str ="LVDS-WUXGA";
     default_bpp = <32>;
     int_clk = <0>;
     late_init = <0>;
     status = "disabled";

And the timing in this way:

    lvds-channel@0 {
         reg = <0>;
         fsl,data-mapping = "spwg"; /* "jeida"; */
         fsl,data-width = <24>;
         crtc = "ipu2-di1";
         status = "okay";
         display-timings {
   timing_wuxga: LVDS-WUXGA {
                clock-frequency = <149992500>;
                hactive = <1920>;
                hback-porch = <20>;
                hfront-porch = <100>;
                hsync-len = <18>;
                hsync-active = <0>;
                vactive = <1200>;
                vback-porch = <4>;
                vfront-porch = <6>;
                vsync-len = <2>;
                vsync-active = <0>;
                de-active = <1>;
                pixelclk-active = <0>;

Now, if I start the kernel with parameter in uboot like:

video=mxcfb0:dev=ldb,1920x1200M@60,if=RGB24,bpp=32 ..

The image start with an high clock (like ~190MHz), this because it use the VESA CVT formula.

It obviously is out of clock, with bad timing etc…, but with the fbset command:

/usr/sbin/fbset  -g 1920 1200 1920 1200 32  -vsync 0 -t 6667 20 100 4 6 18 2

I get a perfect image.

Point: until the device is not started, and the fbset executed I get a bad image, but after executing this command everything is configured correctly.

If i remove the uboot param:


The default parameter is taken from device tree, I get the correct fbset configuration:

mode "1920x1200-60"
    # D: 149.993 MHz, H: 72.883 kHz, V: 60.134 Hz
    geometry 1920 1200 1920 2400 32
    timings 6667 20 100 4 6 18 2
    rgba 8/16,8/8,8/0,8/24

But the image is not good (see attached image).

Executing fbset command in this case doesn’t change anything, the image is bad.

I think that is a clock problem or something like this, the timing correct.

Question: What the VESA CVT formula change other than timing and resolution? How I can set it in devicetree or in uboot? There is some clock change that I can made?

HI @kyakan

Thanks for writing to the Toradex Community!
Is this issue related to this one?

Thanks and best regards,


the post indicated was mine, and is related to the same issue.

But I’m still no found the solution.

So I tried to compress the information in this post hoping that someone can point me.

Hi @kyakan

Thanks for the Information.

I am afraid that we cannot help you on this without having the hardware in our lab. Could you contact the local sales team and bring up this issue there?

Thanks and best regards,