Add pps-gpio

Technical Support
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1

Hello,
I am having issues with pps-gpio driver. I want to have pps signal from GPS connected to the GPIO4_14 (sodimm 133) and use chrony as NTP server for my system. I have created the following patch that should add pps-gpio to the device tree.

diff --git a/arch/arm/boot/dts/imx6ull-colibri-wifi-iris.dts b/arch/arm/boot/dts/imx6ull-colibri-wifi-iris.dts
index 966d02a07b1c..8cee66209932 100644
--- a/arch/arm/boot/dts/imx6ull-colibri-wifi-iris.dts
+++ b/arch/arm/boot/dts/imx6ull-colibri-wifi-iris.dts
@@ -13,4 +13,45 @@
 	compatible = "toradex,colibri-imx6ull-wifi-iris",
 		     "toradex,colibri-imx6ull",
 		     "fsl,imx6ull";
+
+	// add PPS node
+	pps {
+		compatible = "pps-gpio";
+		pinctrl-0 = <&pinctrl_pps>;
+		gpios = <&gpio4 14 GPIO_ACTIVE_HIGH>;
+		assert-falling-edge;
+		pinctrl-names = "default";
+		status = "okay";
+	};
+	
+	pinctrl_pps: pinctrl_pps-grp {
+		fsl,pins = <
+			MX6UL_PAD_NAND_CE1_B__GPIO4_IO14    0x1b0b1 /* SODIMM 133 */
+		>;
+	};
+};
+
+&usbotg1 {
+	dr_mode = "host";
+	status = "okay";
+	/delete-property/srp-disable;
+	/delete-property/hnp-disable;
+	/delete-property/adp-disable;
+	/delete-property/extcon;
+};
+
+&usbotg2 {
+	status = "okay";
+};
+
+&pinctrl_gpio1{
+	fsl,pins = <
+		MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25	0x10b0 /* SODIMM 77 */
+		MX6UL_PAD_JTAG_TCK__GPIO1_IO14		0x70a0 /* SODIMM 99 */
+		MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24	0x10b0 /* SODIMM 135 */
+		MX6UL_PAD_UART3_CTS_B__GPIO1_IO26	0x10b0 /* SODIMM 100 */
+		MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15	0x70a0 /* SODIMM 102 */
+		MX6UL_PAD_ENET1_RX_ER__GPIO2_IO07	0x10b0 /* SODIMM 104 */
+		MX6UL_PAD_UART3_RTS_B__GPIO1_IO27	0x10b0 /* SODIMM 186 */
+	>;
 };

The device is created, but it looks like the pin is not asserted to the device because I still can access the pin using the gpiod tool (i expect that the pin will not be accessible).

I did not make any other changes to the kernel and the default defconfig have the PPS and PPS_CLIENT_GPIO enabled.

Did I miss anything in DTS configuration or it is the problem somewhere else?

I have attached dmesg log, chronyc log, and gpiomon output if it helps.

I will be gratefull for any suggestion.

Best wishes,
Tomas.link text

2

Update:
Hello again. It turned out, that my previous answer was not correct eather. It started working because I updated only the dtb file using the ubiupdatevol.

The problem was that even that I specified that I am using the Iris board, the Tezi image was still deployed with Eval dtb files. So when I did the full flash, the issue was back. I had to create the colibri-imx6ull-extra.inc file with the following content:

TORADEX_PRODUCT_IDS[0036] = "imx6ull-colibri-iris.dtb"
TORADEX_PRODUCT_IDS[0040] = "imx6ull-colibri-wifi-iris.dtb"
TORADEX_PRODUCT_IDS[0044] = "imx6ull-colibri-iris.dtb"
TORADEX_PRODUCT_IDS[0045] = "imx6ull-colibri-wifi-iris.dtb"

KERNEL_DEVICETREE = "imx6ull-colibri-wifi-iris.dtb imx6ull-colibri-iris.dtb"

and the file was included at the end of local.conf. when I did this the tezi was created correctly and everything started to work.

The resulting dts configuration looks like this:

/ {
	model = "Toradex Colibri iMX6ULL 512MB on Colibri Iris";
	compatible = "toradex,colibri-imx6ull-wifi-iris",
		     "toradex,colibri-imx6ull",
		     "fsl,imx6ull";

	// add PPS node
	pps {
		compatible = "pps-gpio";
		gpios = <&gpio4 14 GPIO_ACTIVE_HIGH>;
		status = "okay";
	};
};

&pinctrl_gpio1 {
	fsl,pins = <
				MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25	0x10b0 /* SODIMM 77 */
				MX6UL_PAD_JTAG_TCK__GPIO1_IO14		0x70a0 /* SODIMM 99 */
				MX6UL_PAD_NAND_CE1_B__GPIO4_IO14	0x10b0 /* SODIMM 133 */
				MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24	0x1b0b1 /* SODIMM 135 */
				MX6UL_PAD_UART3_CTS_B__GPIO1_IO26	0x10b0 /* SODIMM 100 */
				MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15	0x70a0 /* SODIMM 102 */
				MX6UL_PAD_ENET1_RX_ER__GPIO2_IO07	0x10b0 /* SODIMM 104 */
				MX6UL_PAD_UART3_RTS_B__GPIO1_IO27	0x10b0 /* SODIMM 186 */
			>;
};

Original answer:

Hi,
I have found my mistake. When I removed pin from free pins of iomuxc node, I forget to add it there.
All I did to solve it was to move pinctrl_pps node from the root node (/) into the referenced iomuxc.

&iomuxc {
	pinctrl_pps: pinctrl_pps-grp {
		fsl,pins = <
			MX6UL_PAD_NAND_CE1_B__GPIO4_IO14    0x1b0b1 /* SODIMM 133 */
		>;
	};
};

Now the pin is asserted to the driver as expected.

The relevant dmesg output.

root@colibri-imx6ull:~# dmesg | grep pps
[    0.101507] imx6ul-pinctrl 20e0000.iomuxc: no groups defined in /soc/aips-bus@2000000/iomuxc@20e0000/pinctrl_ppsp
[    0.343501] pps_core: LinuxPPS API ver. 1 registered
[    0.343541] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
[    1.688832] pps pps0: new PPS source ptp0
[    2.062215] pps_ldisc: PPS line discipline registered
[    2.085209] pps pps1: new PPS source pps.-1
[    2.092898] pps pps1: Registered IRQ 178 as PPS source
[   18.154052] pps pps2: new PPS source acm0
[   18.164019] pps pps2: source "/dev/ttyACM0" added
3

Hello DarkMooN,

sorry for not being faster then you by yourself.
But great that you could fix it.
Best regards,

Matthias