Thank you bhuvan.tx and stefan.tx.
For now, I have this set of configurations of device-tree elements, which enabled the following signals:
- /dev/spidev0.0
- /dev/spidev0.1
- /dev/spidev0.3
- /dev/spidev1.0
- /dev/spidev1.1
- /dev/spidev1.2
- /dev/spidev1.3
The /dev/spidev2.0 and /dev/spidev2.1 does not appear. What could be the cause?
The /dev/spidev3.0 and /dev/spidev3.1 does appear, but it does not work.
I’ve tried to use it with the spidev_test application and a logic analyzer, with no success.
Here are my corresponding files:
vf-colibri.dsti
/*
* Copyright 2014 Toradex AG
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
/ {
reg_module_3v3: regulator-module-3v3 {
compatible = "regulator-fixed";
regulator-name = "+V3.3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_module_3v3_avdd: regulator-module-3v3-avdd {
compatible = "regulator-fixed";
regulator-name = "+V3.3_AVDD_AUDIO";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
&adc0 {
status = "okay";
vref-supply = <®_module_3v3_avdd>;
};
&adc1 {
status = "okay";
vref-supply = <®_module_3v3_avdd>;
};
&can0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan0>;
status = "disabled";
};
&can1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
status = "disabled";
};
&clks {
assigned-clocks = <&clks VF610_CLK_ENET_SEL>,
<&clks VF610_CLK_ENET_TS_SEL>;
assigned-clock-parents = <&clks VF610_CLK_ENET_50M>,
<&clks VF610_CLK_ENET_50M>;
};
&dspi0 {
bus-num=<0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dspi0>;
status = "okay";
};
&dspi1 {
bus-num = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dspi1>;
status = "okay";
};
&dspi2 {
bus-num = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dspi2>;
status = "okay";
};
&dspi3 {
bus-num = <3>;
pinctrl-names = "default";
pin-ctrl-0 = <&pinctrl_dspi3>;
status = "okay";
};
&edma0 {
status = "okay";
};
&fec1 {
phy-mode = "rmii";
phy-supply = <®_module_3v3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
};
&i2c0 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>;
};
&nfc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nfc>;
status = "okay";
nand@0 {
compatible = "fsl,vf610-nfc-nandcs";
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
nand-bus-width = <8>;
nand-ecc-mode = "hw";
nand-ecc-strength = <32>;
nand-ecc-step-size = <2048>;
nand-on-flash-bbt;
};
};
&pwm0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm0_a &pinctrl_pwm0_c>;
};
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1_b &pinctrl_pwm1_d>;
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
};
&usbdev0 {
disable-over-current;
dr_mode = "otg";
status = "okay";
};
&usbmisc0 {
status = "okay";
};
&usbmisc1 {
status = "okay";
};
&usbphy0 {
status = "okay";
};
&usbphy1 {
status = "okay";
};
&iomuxc {
vf610-colibri {
pinctrl_flexcan0: can0grp {
fsl,pins = <
VF610_PAD_PTB14__CAN0_RX 0x31F1
VF610_PAD_PTB15__CAN0_TX 0x31F2
>;
};
pinctrl_flexcan1: can1grp {
fsl,pins = <
VF610_PAD_PTB16__CAN1_RX 0x31F1
VF610_PAD_PTB17__CAN1_TX 0x31F2
>;
};
pinctrl_additionalgpio: additionalgpios {
fsl,pins = <
VF610_PAD_PTA12__GPIO_5 0x22ed
VF610_PAD_PTA17__GPIO_7 0x22ed
VF610_PAD_PTA20__GPIO_10 0x22ed
VF610_PAD_PTA21__GPIO_11 0x22ed
VF610_PAD_PTA30__GPIO_20 0x22ed
VF610_PAD_PTA31__GPIO_21 0x22ed
VF610_PAD_PTB6__GPIO_28 0x22ed
VF610_PAD_PTB7__GPIO_29 0x22ed
VF610_PAD_PTB12__GPIO_34 0x22ed
VF610_PAD_PTB13__GPIO_35 0x22ed
VF610_PAD_PTB16__GPIO_38 0x22ed
VF610_PAD_PTB17__GPIO_39 0x22ed
VF610_PAD_PTC1__GPIO_46 0x22ed
VF610_PAD_PTC2__GPIO_47 0x22ed
VF610_PAD_PTC3__GPIO_48 0x22ed
VF610_PAD_PTC5__GPIO_50 0x22ed
VF610_PAD_PTC6__GPIO_51 0x22ed
VF610_PAD_PTC7__GPIO_52 0x22ed
VF610_PAD_PTC8__GPIO_53 0x22ed
VF610_PAD_PTD26__GPIO_68 0x22ed
VF610_PAD_PTD25__GPIO_69 0x22ed
VF610_PAD_PTD24__GPIO_70 0x22ed
VF610_PAD_PTB23__GPIO_93 0x22ed
VF610_PAD_PTB26__GPIO_96 0x22ed
VF610_PAD_PTB28__GPIO_98 0x22ed
VF610_PAD_PTC30__GPIO_103 0x22ed
VF610_PAD_PTA7__GPIO_134 0x22ed
>;
};
pinctrl_dspi0: dspi0grp {
fsl,pins = <
VF610_PAD_PTC0__DSPI0_CS3 0x33e3
VF610_PAD_PTB18__DSPI0_CS1 0x33e3
VF610_PAD_PTB19__DSPI0_CS0 0x33e3
VF610_PAD_PTB20__DSPI0_SIN 0x33e3
VF610_PAD_PTB21__DSPI0_SOUT 0x33e3
VF610_PAD_PTB22__DSPI0_SCK 0x33e3
>;
};
pinctrl_dspi1: dspi1grp {
fsl,pins = <
VF610_PAD_PTD2__DSPI1_CS3 0x33e3
VF610_PAD_PTD3__DSPI1_CS2 0x33e3
VF610_PAD_PTD4__DSPI1_CS1 0x33e3
VF610_PAD_PTD5__DSPI1_CS0 0x33e3
VF610_PAD_PTD6__DSPI1_SIN 0x33e3
VF610_PAD_PTD7__DSPI1_SOUT 0x33e3
VF610_PAD_PTD8__DSPI1_SCK 0x33e3
>;
};
pinctrl_dspi2: dspi2grp {
fsl,pins = <
VF610_PAD_PTD31__DSPI2_CS1 0x33e3
VF610_PAD_PTD30__DSPI2_CS0 0x33e3
VF610_PAD_PTD29__DSPI2_SIN 0x33e3
VF610_PAD_PTD28__DSPI2_SOUT 0x33e3
VF610_PAD_PTD27__DSPI2_SCK 0x33e3
>;
};
pinctrl_dspi3: dspi3grp {
fsl,pins = <
VF610_PAD_PTD9__DSPI3_CS1 0x33e3
VF610_PAD_PTD10__DSPI3_CS0 0x33e3
VF610_PAD_PTD11__DSPI3_SIN 0x33e3
VF610_PAD_PTD12__DSPI3_SOUT 0x33e3
VF610_PAD_PTD13__DSPI3_SCK 0x33e3
>;
};
pinctrl_esdhc1: esdhc1grp {
fsl,pins = <
VF610_PAD_PTA24__ESDHC1_CLK 0x31ef
VF610_PAD_PTA25__ESDHC1_CMD 0x31ef
VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef
VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef
VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef
VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef
VF610_PAD_PTB20__GPIO_42 0x219d
>;
};
pinctrl_fec1: fec1grp {
fsl,pins = <
VF610_PAD_PTA6__RMII_CLKOUT 0x30d2
VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2
VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3
VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1
VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1
VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1
VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1
VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2
VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2
VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2
>;
};
pinctrl_gpio_bl_on: gpio_bl_on {
fsl,pins = <
VF610_PAD_PTC0__GPIO_45 0x22ef
>;
};
pinctrl_i2c0: i2c0grp {
fsl,pins = <
VF610_PAD_PTB14__I2C0_SCL 0x37ff
VF610_PAD_PTB15__I2C0_SDA 0x37ff
>;
};
pinctrl_nfc: nfcgrp {
fsl,pins = <
VF610_PAD_PTD23__NF_IO7 0x28df
VF610_PAD_PTD22__NF_IO6 0x28df
VF610_PAD_PTD21__NF_IO5 0x28df
VF610_PAD_PTD20__NF_IO4 0x28df
VF610_PAD_PTD19__NF_IO3 0x28df
VF610_PAD_PTD18__NF_IO2 0x28df
VF610_PAD_PTD17__NF_IO1 0x28df
VF610_PAD_PTD16__NF_IO0 0x28df
VF610_PAD_PTB24__NF_WE_B 0x28c2
VF610_PAD_PTB25__NF_CE0_B 0x28c2
VF610_PAD_PTB27__NF_RE_B 0x28c2
VF610_PAD_PTC26__NF_RB_B 0x283d
VF610_PAD_PTC27__NF_ALE 0x28c2
VF610_PAD_PTC28__NF_CLE 0x28c2
>;
};
pinctrl_pwm0_a: pwm0agrp {
fsl,pins = <
VF610_PAD_PTB0__FTM0_CH0 0x1182
>;
};
pinctrl_pwm0_c: pwm0cgrp {
fsl,pins = <
VF610_PAD_PTB1__FTM0_CH1 0x1182
>;
};
pinctrl_pwm1_b: pwm1bgrp {
fsl,pins = <
VF610_PAD_PTB8__FTM1_CH0 0x1182
>;
};
pinctrl_pwm1_d: pwm1dgrp {
fsl,pins = <
VF610_PAD_PTB9__FTM1_CH1 0x1182
>;
};
pinctrl_uart0: uart0grp {
fsl,pins = <
VF610_PAD_PTB10__UART0_TX 0x21a2
VF610_PAD_PTB11__UART0_RX 0x21a1
VF610_PAD_PTB12__UART0_RTS 0x21a2
VF610_PAD_PTB13__UART0_CTS 0x21a1
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
VF610_PAD_PTB4__UART1_TX 0x21a2
VF610_PAD_PTB5__UART1_RX 0x21a1
>;
};
pinctrl_usbc_det: gpio_usbc_det {
fsl,pins = <
VF610_PAD_PTC29__GPIO_102 0x22ed
>;
};
};
};
vf-colibri-eval-v3.dtsi
/*
* Copyright 2014 Toradex AG
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#include <dt-bindings/input/input.h>
/ {
chosen {
stdout-path = "serial0:115200n8";
};
aliases {
ethernet0 = &fec1;
ethernet1 = &fec0;
};
clk16m: clk16m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <16000000>;
};
extcon_usbc_det: usbc_det {
compatible = "linux,extcon-usb-gpio";
debounce = <25>;
id-gpio = <&gpio3 6 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbc_det>;
status = "disabled";
};
reg_3v3: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_5v0: regulator-5v0 {
compatible = "regulator-fixed";
regulator-name = "5V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
};
&can0 {
status = "disabled";
};
&can1 {
status = "okay";
};
&dspi0 {
status = "okay";
spidev00: dspi0@0 {
status = "okay";
compatible = "spidev";
reg = <0>;
spi-max-frequency = <50000000>;
};
spidev01: dspi0@1 {
status = "okay";
compatible = "spidev";
reg = <1>;
spi-max-frequency = <50000000>;
};
spidev03: dspi0@3 {
status = "okay";
compatible = "spidev";
reg = <3>;
spi-max-frequency = <50000000>;
};
};
&dspi1 {
status = "okay";
spidev10: dspi1@0 {
status = "okay";
compatible = "spidev";
reg = <0>;
spi-max-frequency = <50000000>;
};
spidev11: dspi1@1 {
status = "okay";
compatible = "spidev";
reg = <1>;
spi-max-frequency = <50000000>;
};
spidev12: dspi1@2 {
status = "okay";
compatible = "spidev";
reg = <2>;
spi-max-frequency = <50000000>;
};
spidev13: dspi1@3 {
status = "okay";
compatible = "spidev";
reg = <3>;
spi-max-frequency = <50000000>;
};
};
&dspi2 {
status = "okay";
spidev20: dspi2@0 {
status = "okay";
compatible = "spidev";
reg = <0>;
spi-max-frequency = <50000000>;
};
spidev21: dspi2@1 {
status = "okay";
compatible = "spidev";
reg = <1>;
spi-max-frequency = <50000000>;
};
};
&dspi3 {
status = "okay";
spidev30: dspi3@0 {
status = "okay";
compatible = "spidev";
reg = <0>;
spi-max-frequency = <50000000>;
};
spidev31: dspi3@1 {
status = "okay";
compatible = "spidev";
reg = <1>;
spi-max-frequency = <50000000>;
};
};
&fec1 {
phy-mode = "rmii";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
status = "okay";
};
&i2c0 {
status = "okay";
/* M41T0M6 real time clock on carrier board */
rtc: m41t0m6@68 {
compatible = "st,m41t00";
reg = <0x68>;
};
};
&i2c1 {
status = "disabled";
};
&pwm0 {
status = "okay";
};
&pwm1 {
status = "okay";
};
®_module_3v3 {
vin-supply = <®_3v3>;
};
&tcon0 {
status = "okay";
};
&uart0 {
status = "okay";
};
&uart1 {
status = "okay";
};
&usbdev0 {
extcon = <&extcon_usbc_det>, <&extcon_usbc_det>;
dr_mode = "host";
};
vfxxx.dtsi
/*
* Copyright 2013 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#include "vf610-pinfunc.h"
#include <dt-bindings/clock/vf610-clock.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
/ {
aliases {
can0 = &can0;
can1 = &can1;
ethernet0 = &fec0;
ethernet1 = &fec1;
serial0 = &uart0;
serial1 = &uart1;
serial4 = &uart4;
serial5 = &uart5;
dspi0 = &dspi0;
dspi1 = &dspi1;
dspi2 = &dspi2;
dspi3 = &dspi3;
gpio0 = &gpio0;
gpio1 = &gpio1;
gpio2 = &gpio2;
gpio3 = &gpio3;
gpio4 = &gpio4;
usbphy0 = &usbphy0;
usbphy1 = &usbphy1;
};
fxosc: fxosc {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
};
sxosc: sxosc {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
};
reboot: syscon-reboot {
compatible = "syscon-reboot";
regmap = <&src>;
offset = <0x0>;
mask = <0x1000>;
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,vf610-soc-bus", "simple-bus";
interrupt-parent = <&gpc>;
ranges;
fsl,rom-revision = <&ocrom 0x80>;
fsl,cpu-count = <&mscm_cpucfg 0x2C>;
fsl,l2-size = <&mscm_cpucfg 0x14>;
nvmem-cells = <&ocotp_cfg0>, <&ocotp_cfg1>;
nvmem-cell-names = "cfg0", "cfg1";
ocrom: ocrom@00000000 {
compatible = "fsl,vf610-ocrom", "syscon";
reg = <0x00000000 0x18000>;
};
ocram0: sram@3f000000 {
compatible = "mmio-sram";
reg = <0x3f000000 0x40000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x3f000000 0x40000>;
stbyram1@0 {
reg = <0x0 0x4000>;
label = "stbyram1";
pool;
};
stbyram2@4000 {
reg = <0x4000 0xc000>;
label = "stbyram2";
pool;
};
};
ocram1: sram@3f040000 {
compatible = "mmio-sram";
reg = <0x3f040000 0x40000>;
};
gfxram0: sram@3f400000 {
compatible = "mmio-sram";
reg = <0x3f400000 0x80000>;
};
/* used by L2 cache */
gfxram1: sram@3f480000 {
compatible = "mmio-sram";
reg = <0x3f480000 0x80000>;
};
aips0: aips-bus@40000000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
mscm_cpucfg: cpucfg@40001000 {
compatible = "fsl,vf610-mscm-cpucfg", "syscon";
reg = <0x40001000 0x800>;
};
mscm_ir: interrupt-controller@40001800 {
compatible = "fsl,vf610-mscm-ir";
reg = <0x40001800 0x400>;
fsl,cpucfg = <&mscm_cpucfg>;
interrupt-controller;
#interrupt-cells = <2>;
};
edma0: dma-controller@40018000 {
#dma-cells = <2>;
compatible = "fsl,vf610-edma";
reg = <0x40018000 0x2000>,
<0x40024000 0x1000>,
<0x40025000 0x1000>;
dma-channels = <32>;
interrupts = <8 IRQ_TYPE_LEVEL_HIGH>,
<9 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "edma-tx", "edma-err";
clock-names = "dmamux0", "dmamux1";
clocks = <&clks VF610_CLK_DMAMUX0>,
<&clks VF610_CLK_DMAMUX1>;
status = "disabled";
};
can0: flexcan@40020000 {
compatible = "fsl,vf610-flexcan";
reg = <0x40020000 0x4000>;
interrupts = <58 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_FLEXCAN0>,
<&clks VF610_CLK_FLEXCAN0>;
clock-names = "ipg", "per";
status = "disabled";
};
uart0: serial@40027000 {
compatible = "fsl,vf610-lpuart";
reg = <0x40027000 0x1000>;
interrupts = <61 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_UART0>;
clock-names = "ipg";
dmas = <&edma0 0 2>,
<&edma0 0 3>;
dma-names = "rx","tx";
status = "disabled";
};
uart1: serial@40028000 {
compatible = "fsl,vf610-lpuart";
reg = <0x40028000 0x1000>;
interrupts = <62 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_UART1>;
clock-names = "ipg";
dmas = <&edma0 0 4>,
<&edma0 0 5>;
dma-names = "rx","tx";
status = "disabled";
};
dspi0: dspi0@4002c000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,vf610-dspi";
reg = <0x4002c000 0x1000>;
interrupts = <67 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_DSPI0>;
clock-names = "dspi";
spi-num-chipselects = <6>;
status = "okay";
};
dspi1: dspi1@4002d000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,vf610-dspi";
reg = <0x4002d000 0x1000>;
interrupts = <68 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_DSPI1>;
clock-names = "dspi";
spi-num-chipselects = <4>;
status = "okay";
};
dspi2: dspi2@400ac000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl, vf610-dspi";
reg = <0x400ac000 0x1000>;
interrupts = <69 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_DSPI2>;
clock-names = "dspi";
spi-num-chipselects = <2>;
status = "okay";
};
dspi3: dspi3@400ad000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,vf610-dspi";
reg = <0x400ad000 0x1000>;
interrupts = <70 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_DSPI3>;
clock-names = "dspi";
spi-num-chipselects = <2>;
status = "okay";
};
sai0: sai@4002f000 {
compatible = "fsl,vf610-sai";
reg = <0x4002f000 0x1000>;
interrupts = <84 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_SAI0>,
<&clks VF610_CLK_SAI0_DIV>,
<&clks 0>, <&clks 0>;
clock-names = "bus", "mclk1", "mclk2", "mclk3";
dma-names = "tx", "rx";
dmas = <&edma0 0 17>,
<&edma0 0 16>;
status = "disabled";
};
sai2: sai@40031000 {
compatible = "fsl,vf610-sai";
reg = <0x40031000 0x1000>;
interrupts = <86 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_SAI2>,
<&clks VF610_CLK_SAI2_DIV>,
<&clks 0>, <&clks 0>;
clock-names = "bus", "mclk1", "mclk2", "mclk3";
dma-names = "tx", "rx";
dmas = <&edma0 0 21>,
<&edma0 0 20>;
status = "disabled";
};
sai3: sai@40032000 {
compatible = "fsl,vf610-sai";
reg = <0x40032000 0x1000>;
interrupts = <87 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_SAI3>,
<&clks VF610_CLK_SAI3_DIV>,
<&clks 0>, <&clks 0>;
clock-names = "bus", "mclk1", "mclk2", "mclk3";
dma-names = "tx", "rx";
dmas = <&edma0 1 9>,
<&edma0 1 8>;
status = "disabled";
};
pit: pit@40037000 {
compatible = "fsl,vf610-pit";
reg = <0x40037000 0x1000>;
interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_PIT>;
clock-names = "pit";
};
pwm0: pwm@40038000 {
compatible = "fsl,vf610-ftm-pwm";
#pwm-cells = <3>;
reg = <0x40038000 0x1000>;
clock-names = "ftm_sys", "ftm_ext",
"ftm_fix", "ftm_cnt_clk_en";
clocks = <&clks VF610_CLK_FTM0>,
<&clks VF610_CLK_FTM0_EXT_SEL>,
<&clks VF610_CLK_FTM0_FIX_SEL>,
<&clks VF610_CLK_FTM0_EXT_FIX_EN>;
status = "disabled";
};
pwm1: pwm@40039000 {
compatible = "fsl,vf610-ftm-pwm";
#pwm-cells = <3>;
reg = <0x40039000 0x1000>;
clock-names = "ftm_sys", "ftm_ext",
"ftm_fix", "ftm_cnt_clk_en";
clocks = <&clks VF610_CLK_FTM1>,
<&clks VF610_CLK_FTM1_EXT_SEL>,
<&clks VF610_CLK_FTM1_FIX_SEL>,
<&clks VF610_CLK_FTM1_EXT_FIX_EN>;
status = "disabled";
};
adc0: adc@4003b000 {
compatible = "fsl,vf610-adc";
reg = <0x4003b000 0x1000>;
interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_ADC0>;
clock-names = "adc";
#io-channel-cells = <1>;
status = "disabled";
fsl,adck-max-frequency = <30000000>, <40000000>,
<20000000>;
};
tcon0: timing-controller@4003d000 {
compatible = "fsl,vf610-tcon";
reg = <0x4003d000 0x1000>;
clocks = <&clks VF610_CLK_TCON0>;
clock-names = "ipg";
status = "disabled";
};
wdoga5: wdog@4003e000 {
compatible = "fsl,vf610-wdt", "fsl,imx21-wdt";
reg = <0x4003e000 0x1000>;
interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_WDT>;
clock-names = "wdog";
status = "disabled";
};
iomuxc: iomuxc@40048000 {
compatible = "fsl,vf610-iomuxc";
reg = <0x40048000 0x1000>;
};
gpio0: gpio@40049000 {
compatible = "fsl,vf610-gpio";
reg = <0x40049000 0x1000 0x400ff000 0x40>;
gpio-controller;
#gpio-cells = <2>;
interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 0 32>;
fsl,gpio-wakeup = <&wakeup 22 0 8>; /* PTB0...PTB7 */
};
gpio1: gpio@4004a000 {
compatible = "fsl,vf610-gpio";
reg = <0x4004a000 0x1000 0x400ff040 0x40>;
gpio-controller;
#gpio-cells = <2>;
interrupts = <108 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 32 32>;
fsl,gpio-wakeup = <&wakeup 1 8 2>, /* PTB11, PTB12 (NMI)*/
<&wakeup 4 10 1>, /* PTB14 */
<&wakeup 6 11 1>; /* PTB16 */
};
gpio2: gpio@4004b000 {
compatible = "fsl,vf610-gpio";
reg = <0x4004b000 0x1000 0x400ff080 0x40>;
gpio-controller;
#gpio-cells = <2>;
interrupts = <109 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 64 32>;
};
gpio3: gpio@4004c000 {
compatible = "fsl,vf610-gpio";
reg = <0x4004c000 0x1000 0x400ff0c0 0x40>;
gpio-controller;
#gpio-cells = <2>;
interrupts = <110 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 96 32>;
fsl,gpio-wakeup = <&wakeup 1 14 1>, /* PTB27 */
<&wakeup 7 15 1>, /* PTC30 */
<&wakeup 29 16 1>; /* PTE20 */
};
gpio4: gpio@4004d000 {
compatible = "fsl,vf610-gpio";
reg = <0x4004d000 0x1000 0x400ff100 0x40>;
gpio-controller;
#gpio-cells = <2>;
interrupts = <111 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 128 7>;
};
anatop: anatop@40050000 {
compatible = "fsl,vf610-anatop", "syscon";
reg = <0x40050000 0x400>;
};
scsc: scsc@40052000 {
compatible = "fsl,vf610-scsc";
reg = <0x40052000 0x1000>;
};
usbphy0: usbphy@40050800 {
compatible = "fsl,vf610-usbphy";
reg = <0x40050800 0x400>;
interrupts = <50 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_USBPHY0>;
fsl,anatop = <&anatop>;
status = "disabled";
};
usbphy1: usbphy@40050c00 {
compatible = "fsl,vf610-usbphy";
reg = <0x40050c00 0x400>;
interrupts = <51 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_USBPHY1>;
fsl,anatop = <&anatop>;
status = "disabled";
};
i2c0: i2c@40066000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,vf610-i2c";
reg = <0x40066000 0x1000>;
interrupts = <71 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_I2C0>;
clock-names = "ipg";
dmas = <&edma0 0 50>,
<&edma0 0 51>;
dma-names = "rx","tx";
status = "disabled";
};
i2c1: i2c@40067000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,vf610-i2c";
reg = <0x40067000 0x1000>;
interrupts = <72 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_I2C1>;
clock-names = "ipg";
dmas = <&edma0 0 52>,
<&edma0 0 53>;
dma-names = "rx","tx";
status = "disabled";
};
wakeup: wkpu@4006a000 {
compatible = "fsl,vf610-wkpu";
reg = <0x4006a000 0x1000>;
interrupts = <92 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_WKPU>;
};
clks: ccm@4006b000 {
compatible = "fsl,vf610-ccm";
reg = <0x4006b000 0x1000>;
clocks = <&sxosc>, <&fxosc>;
clock-names = "sxosc", "fxosc";
#clock-cells = <1>;
};
usbdev0: usb@40034000 {
compatible = "fsl,vf610-usb";
reg = <0x40034000 0x800>;
interrupts = <75 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_USBC0>;
fsl,usbphy = <&usbphy0>;
fsl,usbmisc = <&usbmisc0 0>;
dr_mode = "peripheral";
status = "disabled";
};
usbmisc0: usb@40034800 {
#index-cells = <1>;
compatible = "fsl,vf610-usbmisc";
reg = <0x40034800 0x200>;
clocks = <&clks VF610_CLK_USBC0>;
status = "disabled";
};
src: src@4006e000 {
compatible = "fsl,vf610-src", "syscon";
reg = <0x4006e000 0x1000>;
interrupts = <96 IRQ_TYPE_LEVEL_HIGH>;
};
gpc: gpc@4006c000 {
compatible = "fsl,vf610-gpc";
reg = <0x4006c000 0x1000>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&mscm_ir>;
};
};
aips1: aips-bus@40080000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
edma1: dma-controller@40098000 {
#dma-cells = <2>;
compatible = "fsl,vf610-edma";
reg = <0x40098000 0x2000>,
<0x400a1000 0x1000>,
<0x400a2000 0x1000>;
dma-channels = <32>;
interrupts = <10 IRQ_TYPE_LEVEL_HIGH>,
<11 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "edma-tx", "edma-err";
clock-names = "dmamux0", "dmamux1";
clocks = <&clks VF610_CLK_DMAMUX2>,
<&clks VF610_CLK_DMAMUX3>;
status = "disabled";
};
ocotp@400a5000 {
compatible = "fsl,vf610-ocotp";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x400a5000 0xCF0>;
clocks = <&clks VF610_CLK_OCOTP>;
ocotp_cfg0: cfg0@410 {
reg = <0x410 0x4>;
};
ocotp_cfg1: cfg1@420 {
reg = <0x420 0x4>;
};
};
snvs0: snvs@400a7000 {
compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
reg = <0x400a7000 0x2000>;
snvsrtc: snvs-rtc-lp {
compatible = "fsl,sec-v4.0-mon-rtc-lp";
regmap = <&snvs0>;
offset = <0x34>;
interrupts = <100 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_SNVS>;
clock-names = "snvs-rtc";
};
};
uart4: serial@400a9000 {
compatible = "fsl,vf610-lpuart";
reg = <0x400a9000 0x1000>;
interrupts = <65 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_UART4>;
clock-names = "ipg";
status = "disabled";
};
uart5: serial@400aa000 {
compatible = "fsl,vf610-lpuart";
reg = <0x400aa000 0x1000>;
interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_UART5>;
clock-names = "ipg";
status = "disabled";
};
ddrmc: ddrmc@400ae000 {
compatible = "fsl,vf610-ddrmc";
reg = <0x400ae000 0x400>;
clocks = <&clks VF610_CLK_DDRMC>;
clock-names = "ddrc";
};
adc1: adc@400bb000 {
compatible = "fsl,vf610-adc";
reg = <0x400bb000 0x1000>;
interrupts = <54 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_ADC1>;
clock-names = "adc";
#io-channel-cells = <1>;
status = "disabled";
fsl,adck-max-frequency = <30000000>, <40000000>,
<20000000>;
};
esdhc0: esdhc@400b1000 {
compatible = "fsl,imx53-esdhc";
reg = <0x400b1000 0x1000>;
interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_IPG_BUS>,
<&clks VF610_CLK_PLATFORM_BUS>,
<&clks VF610_CLK_ESDHC0>;
clock-names = "ipg", "ahb", "per";
status = "disabled";
};
esdhc1: esdhc@400b2000 {
compatible = "fsl,imx53-esdhc";
reg = <0x400b2000 0x1000>;
interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_IPG_BUS>,
<&clks VF610_CLK_PLATFORM_BUS>,
<&clks VF610_CLK_ESDHC1>;
clock-names = "ipg", "ahb", "per";
status = "disabled";
};
usbmisc1: usb@400b4800 {
#index-cells = <1>;
compatible = "fsl,vf610-usbmisc";
reg = <0x400b4800 0x200>;
clocks = <&clks VF610_CLK_USBC1>;
status = "disabled";
};
ftm: ftm@400b8000 {
compatible = "fsl,ftm-timer";
reg = <0x400b8000 0x1000 0x400b9000 0x1000>;
interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "ftm-evt", "ftm-src",
"ftm-evt-counter-en", "ftm-src-counter-en";
clocks = <&clks VF610_CLK_FTM2>,
<&clks VF610_CLK_FTM2_EXT_FIX_EN>;
status = "disabled";
};
qspi1: quadspi@400c4000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,vf610-qspi";
reg = <0x400c4000 0x1000>, <0x50000000 0x10000000>;
reg-names = "QuadSPI", "QuadSPI-memory";
interrupts = <25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_QSPI1_EN>,
<&clks VF610_CLK_QSPI1>;
clock-names = "qspi_en", "qspi";
status = "disabled";
};
dac0: dac@400cc000 {
compatible = "fsl,vf610-dac";
reg = <0x400cc000 1000>;
interrupts = <55 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "dac";
clocks = <&clks VF610_CLK_DAC0>;
status = "disabled";
};
dac1: dac@400cd000 {
compatible = "fsl,vf610-dac";
reg = <0x400cd000 1000>;
interrupts = <56 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "dac";
clocks = <&clks VF610_CLK_DAC1>;
status = "disabled";
};
fec0: ethernet@400d0000 {
compatible = "fsl,mvf600-fec";
reg = <0x400d0000 0x1000>;
interrupts = <78 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_ENET0>,
<&clks VF610_CLK_ENET0>,
<&clks VF610_CLK_ENET>;
clock-names = "ipg", "ahb", "ptp";
status = "disabled";
};
fec1: ethernet@400d1000 {
compatible = "fsl,mvf600-fec";
reg = <0x400d1000 0x1000>;
interrupts = <79 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_ENET1>,
<&clks VF610_CLK_ENET1>,
<&clks VF610_CLK_ENET>;
clock-names = "ipg", "ahb", "ptp";
status = "disabled";
};
can1: flexcan@400d4000 {
compatible = "fsl,vf610-flexcan";
reg = <0x400d4000 0x4000>;
interrupts = <59 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_FLEXCAN1>,
<&clks VF610_CLK_FLEXCAN1>;
clock-names = "ipg", "per";
status = "disabled";
};
nfc: nand@400e0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,vf610-nfc";
reg = <0x400e0000 0x4000>;
interrupts = <83 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_NFC>;
clock-names = "nfc";
status = "disabled";
};
esw: l2-switch@400e8000 {
compatible = "fsl,eth-switch";
reg = <0x400e8000 0x1000 0x400d0000 0x2000>;
interrupts = <82 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_ESW>,
<&clks VF610_CLK_ENET>,
<&clks VF610_CLK_ENET0>,
<&clks VF610_CLK_ENET1>;
clock-names = "esw", "enet", "enet0", "enet1";
status = "disabled";
};
};
adc_hwmon: iio_hwmon {
compatible = "iio-hwmon";
io-channels = <&adc0 16>, <&adc1 16>;
};
};
};
Thanks for your attention and your help.
