Access to a GPIO from multiple cores

Is it safe to access the same GPIO pin from both the cores of a VF61 in the following scenario?

  1. A5 core sets the pin to 0 or 1 state (the pin is an output for A5 core)
  2. M4 core reads the level of the pin (the pin is an input for M4 core).
  3. no mutex, resource lock mechanisms, or similar is implemented

Hi @vix ,

If you only change the level (Gpio_SetLevel() API) this is safe (atomic) as it has Set and Clear registers (no read modify write operations). But a direction change is not atomic.

Reading the Level from M4 actually is always atomic, so i’m not sure why you were asking it together with Point 1.

Lock mechanism would only be needed if you want to change direction of GPIOs from both A5 and M4, but for level changes or reads there is no problem.