Access i.MX 6ULL registers directly

Technical Support
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1

Hi,

I have discovered that there is delay between CS falling edge to first SPI clock, and SPI last clock to CS rising edge. I want those delays to go. Similar questions have been already asked, but I could not find any solution.

I have tested SPI comunication with this code:

{

int spi_fd, i;
uint32_t mode;
uint8_t bits;
uint32_t speed;

char buff_tx[BUFF_SIZE];
char buff_rx[BUFF_SIZE];
struct spi_ioc_transfer buff;

speed = 1000000;
bits = 16;
mode = 0;

spi_fd = open("/dev/spidev0.0", O_RDWR | O_NONBLOCK);

memset(buff_tx, 0x65, BUFF_SIZE);

if(spi_fd < 0)
	return -1;
ioctl(spi_fd, SPI_IOC_WR_MODE32, &mode);
ioctl(spi_fd, SPI_IOC_RD_MODE32, &mode);
ioctl(spi_fd, SPI_IOC_WR_BITS_PER_WORD, &bits);
ioctl(spi_fd, SPI_IOC_RD_BITS_PER_WORD, &bits);
ioctl(spi_fd, SPI_IOC_WR_MAX_SPEED_HZ, &speed);
ioctl(spi_fd, SPI_IOC_RD_MAX_SPEED_HZ, &speed);

ioctl(spi_fd, SPI_IOC_MESSAGE(1), &buff);

close(spi_fd);

return 0;

}

With spi_ioc_transfer I can change data speed, SPI mode, bits per word. But what about other SPI parameters?
How do I change for example Sample Period Control Register (ECSPIx_PERIODREG) on the i.Mx6ull processor? Is there a struct that can access this register?

Best regards,

Taras

2

Hi @Taras

Thanks for contacting the Toradex Support.

I have discovered that there is delay between CS falling edge to first SPI clock, and SPI last clock to CS rising edge. I want those delays to go. Similar questions have been already asked, but I could not find any solution.

What is the duration of the delay? What is your communication speed?

How do I change for example Sample Period Control Register (ECSPIx_PERIODREG) on the i.Mx6ull processor? Is there a struct that can access this register?

Which exact parameters are you talking about?
You can use the tool devmem2 for accessing he register of iMX6ULL processor.

Best regards,
Jaski

3

Hi,
Sorry for late answer. Speed is 10MHz, delays are 200µs and 400µs.
I am talking about ECSPI registers from i.MX 6ULL Applications Processor
Reference Manual. There is a parameter in ECSPIx_PERIODREG register which defines how many SPI clocks will be inserted between the chip select’s active edge and the first SPI clock edge.

I will try this tool, thank you.

Best regards,
Taras

4

Hi
Thanks for your Input. Please let us know it works.

Best regards,
Jaski