Access 16-bit parallel address bus with A0 used as WEH

Technical Support
, , , ,
1

One of our external devices can be interfaced directly as a memory mapped peripheral. It can be configured for 8-bit or 16-bit parallel operation

Citing the Hardware Design Guide

The A0 signal is not needed in 16-bit parallel operating mode, as 16 bits are addressed instead of 8 bits. If there is need for writing one byte at the time signals WEH and WEL can be used to enable writing to the high or low byte respectively. If both are enabled both bytes are written.

This is the function table:

| WEL (WE) | WEH (A0) | OE       | Comment             |
+----------+----------+----------+---------------------+
|  LOW     | HIGH     | X        | D[0..7] is written  |
|  HIGH    | LOW      | X        | D[8..15] is written |
|  LOW     | LOW      | X        | D[0..15] is written |
|  HIGH    | HIGH     | LOW      | D[0..15] is read    |

Using the sram driver as explained in Accessing External Memory Bus (EIM) on iMX6 via memory map writing D[0…15] is no problem as 16bit addresses always have A0 set to 0 and we are not interested in single byte writes.

But reading is impossible.

Is there any Linux Kernel driver which is compatible with this kind of external memory bus? Or can EIM_DA0 be configured in a way that it functions as WE?

2

Hi

What Hardware Design Guide? I assume this is the attached memory mapped peripheral and also the function table is a description of the peripheral.

I don’t think that the i.MX 6 has such a functionality. The i.MX 6 EIM_EB[0:3] signals provide the functionality to have 8 bit access to memory on a 16 or 32 bit wide data bus.

Using the sram driver…
Is there any Linux Kernel driver which is compatible with this kind of external memory bus?

Note that the driver’s only responsibility is to set the EIM configuration registers. After that your external memory is part of the physical address space and access to the memory works directly and does not involve the driver.

The i.MX 6 reference manual is the guide to consult.

One possibility would be to use the EIM_RW signal for both WEL and WEH and to use the EIM_OE for OE.

For writes EIM_RW goes low and EIM_OE stays high. that way you have your ‘D[0…15] is written’ condition.
For reads EIM_RW stays high and EIM_OE goes low. that way you have your ‘D[0…15] is read’ condition.

Drawback is that the WEH signal in the write case gets valid only at the the time EIM_RW is asserted while usually addresses are valid a bit earlier.

Max

3

What Hardware Design Guide? I assume this is the attached memory mapped peripheral and also the function table is a description of the peripheral.

Yes, your assumption is correct.

Note that the driver’s only responsibility is to set the EIM configuration registers. After that your external memory is part of the physical address space and access to the memory works directly and does not involve the driver.

Ok, I wasn’t aware of that fact. This explains a lot :wink:

One possibility would be to use the EIM_RW signal for both WEL and WEH and to use the EIM_OE for OE.

This is exactly the way we will go now. I just wanted to rule out any software solutions before changing the hardware. Thank you.