we use an SPI-Streaming between Apalis T30 Spi0 and 10 externel Boards connected to the Apalis-Spi-Bus.
The Streaming will transmit/Receive 56Bytes with each of the externel Boards connected to the Bus.
So we adapt the spi-tegra driver to use the tegra-DMA to handle this, and after each complete(), we change the Chip Selects over an externel Multiplexing Chip.
My Question is: How can i catch the Transmit End in a fast way than the Rx-Complete Interrupt from the Tegra-DMA-Engine? Is the FIQ an Option to do that instead of IRQ?
If yes, should i change the Bit 7 in this Register “SEC_ICTLR_CPU_IEP_CLASS_0”?
I will be glad about each Feedback.