Where to setup a Fast IRQ on Apalis T30?

Hi all,
we use an SPI-Streaming between Apalis T30 Spi0 and 10 externel Boards connected to the Apalis-Spi-Bus.
The Streaming will transmit/Receive 56Bytes with each of the externel Boards connected to the Bus.
So we adapt the spi-tegra driver to use the tegra-DMA to handle this, and after each complete(), we change the Chip Selects over an externel Multiplexing Chip.
My Question is: How can i catch the Transmit End in a fast way than the Rx-Complete Interrupt from the Tegra-DMA-Engine? Is the FIQ an Option to do that instead of IRQ?
If yes, should i change the Bit 7 in this Register “SEC_ICTLR_CPU_IEP_CLASS_0”?

I will be glad about each Feedback.
Many Thanks

As far as I remember there is no FIQ infrastructure in Linux so yes you may use it as you please but you also would have to all do it manually.

Have a look at Free Electron’s blog post about the thematic to get a better understanding.

Dear Mr Ziswiler,
Many thanks for your Fast Reponse.
1 - If i understood you, you mean i should only set the Bit 7 for DTV in “SEC_ICTLR_CPU_IEP_CLASS_0”, like the Description in the Reference Manual page 64, and the Interrupt Request registred in the spi-tegra-driver will be fast enough?
2 - Is there for each CPU a Register naming “SEC_ICTLR_CPU_IEP_CLASS_0”?
Many thanks for your Help
Tagangout