VF61 - share memory between M4 and A5 on Linux

Could you tell me if the TCMU memory on Colibri VF61 module is used by Linux? Or is it completely available for M4? I’d like to write data in TMCU memory from Cortex-M4 and read that from the Linux side (userspace). The A5 never writes.

I’d like to share a small area of memory, I would say 1KB between M4 and A5… M4 writes and A5 reads. Do you think the TCMU area is a good and safe option for that? On the Linux side (userspace) I will map this area with mmap.

Regards…

Hi @ives!

Thanks for contacting us.

Unfortunately, it seems you cannot share memory this way.
If you try to access the M4 memory on Linux, the MMU will give you a segmentation fault.

The M4 TCM is isolated and can’t be directly accessed by Linux.

Even if you run your M4 application on RAM and write to that, you wouldn’t be able to access the data on Linux, since the memory gets reserved for each core. Also, running the M4 firmware from RAM reduces performance drastically.

The way to communicate between cores is by using RPMsg. There’s some documentation on using RPMsg with FreeRTOS on the VF61 here. If you use the tty RPMsg driver, you could even read M4 data from userspace in a very similar way that you’d read a serial port.

Basically, there’s a peripheral inside the SoC which is responsible for these memory transfers. RPMsg uses virtio which leverages that to accomplish communication.

Hi @gustavo.tx! Thanks for your message.

I agree with you that the best way is by using RPMsg.

However, I already have an app on the field for almost 2 years that shares memory between M4 and A5, without RPMsg. I’ve never got a segmentation fault, so it seems TCMU is not isolated from Linux, I can read the TCMU from Linux.

I’d like to know if there is any problem sharing memory this way and if I should change the source code and use RPMsg for that. I’m not sure if the TCMU memory is used by Linux or is completely available for M4. I haven’t modified the device tree.

Hi @ives!

You’re right, Linux indeed has access to the TCMU since you can load an M4 firmware from Linux (or U-Boot).

The TCMU should be completely available to M4, which has direct access to it, as mentioned in section 3.11.1 here.

I think it depends. How did you implement this memory sharing? NXP recommends using RPMsg, but I don’t see any issues if you’re only reading from the TCM.

Hi @ives!

You’re right, Linux indeed has access to the TCMU since you can load an M4 firmware from Linux (or U-Boot).

The TCMU should be completely available to M4, which has direct access to it, as mentioned in section 3.11.1 here.

I think it depends. How did you implement this memory sharing? NXP recommends using RPMsg, but I don’t see any issues if you’re only reading from the TCM.

Hi @gustavo.tx.

On Cortex M4 I declare a pointer pointing to the the address on TMCU that Linux will read. Take a look:

// Declare a pointer to a TCMU area
volatile uint32_t * tcmuCounter = (volatile uint32_t *) 0x3f800000;

// Initialize the variable on the TCMU area 
*tcmuCounter = 0;

On Cortex A5 (Linux), I open the file “/dev/mem”, map the physical address 0x3f800000 with mmap and read the value.

Please, let me know if you need more information.

Regards!