Hi ,
I used Verdin Development board to enable the Feature on the Coretex M7 CPU.
when i changed to IVY plus, i faced one problem that UART4 is not brough out in IVY PLus.
So i need to change it to UART1.
Can you guide me on this.
Thanks
Ramesh.
Hi, I’m the Toradex AI Assistant.
I might make mistakes or occasionally get you wrong. Our support team will step in if needed.
I’d be glad to help! Could you let me know which OS and version you are using on your Verdin module?
To provide the most accurate guidance for changing from UART4 to UART1 for Cortex-M7 communication on the Ivy Plus carrier board, I need to know:
You can get this information by running the tdx-info command on your device. More details about this command are available at: Getting Device Information with Tdx-Info | Toradex Developer Center
Once I know your platform details, I can provide specific guidance on:
Best regards, Toradex AI Assistant.
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If I answered your question, please tick the “Solution” checkbox.
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Hi,
Here is the information.
My aim is to Send and receive data in the UART1 from CM7.
Software summary
------------------------------------------------------------
Bootloader: U-Boot
Kernel version: 6.6.54-rt44-7.1.0-devel-gd344e3ea493b #1 SMP PREEMPT_R
T Thu Oct 31 16:17:44 UTC 2024
Kernel command line: root=PARTUUID=15928c7e-02 ro rootwait console=tty1 con
sole=ttymxc2,115200
Distro name: NAME=“TDX Wayland with XWayland RT”
Distro version: VERSION_ID=7.1.0-devel-20241209103856-build.0
Distro variant: -
Hostname: verdin-imx8mp-15290727
------------------------------------------------------------
Hardware info
------------------------------------------------------------
HW model: Toradex Verdin iMX8M Plus on Ivy
Toradex version: 0063 V1.1B
Serial number: 15290727
Processor arch: aarch64
------------------------------------------------------------
Perfect! Now I can help you migrate your Cortex-M7 UART communication from UART4 to UART1 on the Ivy Plus carrier board with your Verdin iMX8M Plus running Torizon OS 7.1.0.
Based on your setup, you’ll need to make changes in three areas:
For Verdin iMX8M Plus, you’ll need to create or modify a device tree overlay to disable UART1 from Linux control so the Cortex-M7 can use it(1). The overlay structure should follow this pattern:
/dts-v1/;
/plugin/;
/ {
compatible = "toradex,verdin-imx8mp-wifi-dahlia",
"toradex,verdin-imx8mp-wifi",
"toradex,verdin-imx8mp",
"fsl,imx8mp";
};
You’ll need to disable UART1 in the Linux device tree by setting its status to “disabled” to prevent conflicts with the Cortex-M7 usage(1).
In your MCUXpresso SDK project, you’ll need to modify the pin mux configuration files. The changes will be in:
pin_mux.c - Update the pin configuration functionspin_mux.h - Update the pin definitionsThe exact pin assignments will depend on which SODIMM pins are available on the Ivy Plus carrier board for UART1 functionality(1).
For Verdin iMX8M Plus, clock configuration changes may be necessary when switching UART peripherals(1). You should verify the clock settings in your MCUXpresso project configuration.
Check Ivy Plus pin availability - Verify which SODIMM pins are brought out on the Ivy Plus for UART1 functionality(2)
Update your MCUXpresso project - Modify the pin mux files to use UART1 instead of UART4
Create device tree overlay - Disable UART1 in Linux to allow Cortex-M7 access
Apply the overlay - Use TorizonCore Builder or the device tree overlay process for Torizon OS(1)
Test the configuration - Load your modified Cortex-M7 firmware and verify UART1 communication
The process follows the same principles described in the Hello World guide for Cortex-M development, but adapted for your specific UART change(1).
Would you like me to provide more specific details about any of these steps, such as the exact pin mux configurations or device tree overlay syntax?
Best regards, Toradex AI Assistant.
Did you like my answer?
If I answered your question, please tick the “Solution” checkbox.
For follow-up questions to me, please use @ToradexAI in your post.
Hi @ramesh.rajagopal , have you successfully enabled UART1 for M7? Is it FreeRTOS or a bare metal application on the M7 core?
Hi Banjamin,
I haven’t finished that yet.
I am not using the freeRTOS.
I am using the example code from SDK and reconfiguring UART 1 from UART4 used int he sample code. The reason changing is IVY+ bard doesnot provide uart4.
one more thing, when i tried to send data from the uart1 , i can see some junk is printing. Though i changed the different all the baud rate setting in the HyperTerminal, it doesnot help .
seems the clock setting i am doing something wrong.
Thanks @ramesh.rajagopal .
Which example code are you working on? Please provide the example path from the SDK. And what is the version of MCU SDK ? NXP’s latest SDK_25_12_00_MIMX8ML8xxxKZ differs from previous versions.
Hi Benjamin,
I am using this
Example code : evkmimx8mp_hello_world_cm7
SDK Version : SDK_25_6_00_MIMX8ML8xxxKZ
Thansk
Ramesh.
Hi @ramesh.rajagopal , the attached patch sets the CM7 debug console from UART4 to UART1. I tested it with SDK_25_06_00_MIMX8ML8xxxKZ/boards/evkmimx8mp/demo_apps/hello_world example.
cm7_uart1_debug_console.patch (3.0 KB)
Hi Benjamin,
It is working now,.
one of the issue with the RS232 to USB conversion.
I used the TTL ( 3.3V) level to USB converter which does not work as it was 5V level from IVY plus as RS232.
For some to use it.
/dts-v1/;
/plugin/;
&uart1 {
status = “disabled”;
pinctrl-0 = <>;
}
Using MCU config tool to generate the pinmux.c /.h
IOMUXC_SetPinMux(IOMUXC_UART1_RXD_UART1_RX, 0U);
IOMUXC_SetPinConfig(IOMUXC_UART1_RXD_UART1_RX,
IOMUXC_SW_PAD_CTL_PAD_DSE(3U) |
IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
IOMUXC_SW_PAD_CTL_PAD_PE_MASK);
IOMUXC_SetPinMux(IOMUXC_UART1_TXD_UART1_TX, 0U);
IOMUXC_SetPinConfig(IOMUXC_UART1_TXD_UART1_TX,
IOMUXC_SW_PAD_CTL_PAD_DSE(3U) |
IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
IOMUXC_SW_PAD_CTL_PAD_PE_MASK);
Replace the UART definition in board.h
#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
#define BOARD_DEBUG_UART_BAUDRATE (115200U)
#define BOARD_DEBUG_UART_BASEADDR UART1_BASE
#define BOARD_DEBUG_UART_INSTANCE (1U)
//#define BOARD_DEBUG_UART_CLK_FREQ (24000000U)
#define BOARD_DEBUG_UART_CLK_FREQ \
(CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart1)) / \
(CLOCK_GetRootPostDivider(kCLOCK_RootUart1)) / 10)
#define BOARD_UART_IRQ UART1_IRQn
#define BOARD_UART_IRQ_HANDLER UART1_IRQHandler
Clockconfig.c
IOMUXC_SetPinMux(IOMUXC_UART1_RXD_UART1_RX, 0U);
IOMUXC_SetPinConfig(IOMUXC_UART1_RXD_UART1_RX,
IOMUXC_SW_PAD_CTL_PAD_DSE(3U) |
IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
IOMUXC_SW_PAD_CTL_PAD_PE_MASK);
IOMUXC_SetPinMux(IOMUXC_UART1_TXD_UART1_TX, 0U);
IOMUXC_SetPinConfig(IOMUXC_UART1_TXD_UART1_TX,
IOMUXC_SW_PAD_CTL_PAD_DSE(3U) |
IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
IOMUXC_SW_PAD_CTL_PAD_PE_MASK);
This way it works for me. Thanks.