Dear @kratabl,
Please excuse the delay in reply.
You are indeed correct in your assumption regarding usdhc3.
Here is the plan to help you create a functioning device tree to use the GPIOs:
1.) We need to make sure that all nodes, which use pinctrl_usdhc3* are disabled. this can be done by checking the whole device tree with a tool called find in devicetree.
2.) Using this tool will show all the .dtsi files (and corresponding lines) which contain the entered pinctrl.
3.) disable all the nodes which use that pinctrl with status = "disabled".
4.) From here you should create a new pinctrl group as GPIOs with help of the imx8mm-pinfunc.h provided by NXP. This file should be contained within your device tree and hold the macros for muxing. As I see it you will have to use these macros for your pinctrl.
#define MX8MM_IOMUXC_NAND_DATA04_GPIO3_IO10 0x11C 0x384 0x000 0x5 0x0
#define MX8MM_IOMUXC_NAND_DATA05_GPIO3_IO11 0x120 0x388 0x000 0x5 0x0
#define MX8MM_IOMUXC_NAND_DATA06_GPIO3_IO12 0x124 0x38C 0x000 0x5 0x0
#define MX8MM_IOMUXC_NAND_DATA07_GPIO3_IO13 0x128 0x390 0x000 0x5 0x0
5.) For your newly created pinctrl group you will also need padcontrols after your macros. We can assume, that the padcontrol is identical to the ones used for a gpio of the same number, such as 0x106 in this example:
pinctrl_gpio1: gpio1grp {
fsl,pins =
<MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x106>; /* SODIMM 206 */
};
Please note, that the padcontrol number could potentially be different, in which case we will have to refer to the reference manual of the NXP SoC.
6.) Eventually your new pinctrl should contain something similar to this:
<MX8MM_IOMUXC_NAND_DATA04_GPIO3_IO10 0x106>;
<MX8MM_IOMUXC_NAND_DATA04_GPIO3_IO11 0x106>;
<MX8MM_IOMUXC_NAND_DATA04_GPIO3_IO12 0x106>;
<MX8MM_IOMUXC_NAND_DATA04_GPIO3_IO13 0x106>;
Please let me know how you fare with this.
Best regards
Collin