Toradex iMX8Q SoM System Controller firmware

I am currently in progress of trying to bringup some hardware with iMX8QX SoM and I was wondering if Toradex had any pre-built and/or source code for a compatible System Controller (SCU) firmware for this SoM module including DCD RAM configuration.

On Toradex github I have found “mx8qx-colibri-scfw-tcm.bin” at this location:

Is this appropriate to use with compatible 4.14.78 (sumo) build? Do you have source code for this SCU firmware that we can customize for our needs?

Hi

Your link to github points to SCFW used for the Colibri iMX8QXP 2GB WB IT V1.0B.

With regards to the sources, please have a look here.

Max

Hi Max,

Thanks for the quick response. When I clicked on the link you have provided for sources I get “Access Denied” error.

Thanks for the support!

Brandon

hi @bjj2282
Now the link should be accessible.

Best regards,
Jaski

Hi @max.tx ,

If we are not able to receive the SCFW Toradex source (or porting kit) can you give us a full list of resource/pin allocation done in the Toradex SCFW.

Hi

The following calls change the ressource allocation in the board file:

    #ifdef DEBUG_UART
        (void) rm_set_resource_movable(SC_PT, SC_R_SC_UART, SC_R_SC_UART,
            SC_FALSE);
        (void) rm_set_pad_movable(pt_sc, SC_P_SCU_GPIO0_00, SC_P_SCU_GPIO0_01,
            SC_FALSE);
    #endif

    (void) rm_set_resource_movable(pt_sc, SC_R_SC_I2C, SC_R_SC_I2C,
        SC_FALSE);
    (void) rm_set_pad_movable(pt_sc, SC_P_PMIC_I2C_SCL, SC_P_PMIC_I2C_SDA,
        SC_FALSE);

    /* 32k standby clock for Wi-Fi */
    (void) rm_set_pad_movable(pt_sc, SC_P_SCU_BOOT_MODE3, SC_P_SCU_BOOT_MODE3,
        SC_TRUE);

Apart from that the resource allocation is identical to the mx8qx_mek board file

        /* Mark all resources as not movable */
        BRD_ERR(rm_set_resource_movable(pt_boot, SC_R_ALL, SC_R_ALL,
            SC_FALSE));
        BRD_ERR(rm_set_pad_movable(pt_boot, SC_P_ALL, SC_P_ALL,
            SC_FALSE));
        
        /* Allocate M4_0 partition */
        BRD_ERR(rm_partition_alloc(pt_boot, &pt_m4_0, SC_FALSE, SC_TRUE,
            SC_FALSE, SC_TRUE, SC_FALSE));
        
        /* Mark all M4_0 subsystem resources as movable */
        BRD_ERR(rm_set_subsys_rsrc_movable(pt_boot, SC_R_M4_0_PID0,
            SC_TRUE));
        BRD_ERR(rm_set_pad_movable(pt_boot,SC_P_ADC_IN3,SC_P_ADC_IN2,
            SC_TRUE));

        /* Keep some resources in the boot partition */
        BRD_ERR(rm_set_resource_movable(pt_boot, SC_R_M4_0_PID1,
            SC_R_M4_0_PID4, SC_FALSE));
        BRD_ERR(rm_set_resource_movable(pt_boot, SC_R_M4_0_MU_0A0,
            SC_R_M4_0_MU_0A3, SC_FALSE));

        /* Move some resources not in the M4_0 subsystem */
        BRD_ERR(rm_set_resource_movable(pt_boot, SC_R_IRQSTR_M4_0,
            SC_R_IRQSTR_M4_0, SC_TRUE));
        BRD_ERR(rm_set_resource_movable(pt_boot, SC_R_M4_1_MU_0A0,
            SC_R_M4_1_MU_0A0, SC_TRUE));
        BRD_ERR(rm_set_resource_movable(pt_boot, SC_R_MU_5B,
            SC_R_MU_5B, SC_TRUE));
        BRD_ERR(rm_set_resource_movable(pt_boot, SC_R_GPT_4,
            SC_R_GPT_4, SC_TRUE));
        BRD_ERR(rm_set_resource_movable(pt_boot, SC_R_CAN_0,
            SC_R_CAN_0, SC_TRUE));

        /* Move some pads not in the M4_0 subsystem */
        BRD_ERR(rm_set_pad_movable(pt_boot, SC_P_FLEXCAN0_RX,
            SC_P_FLEXCAN0_TX, SC_TRUE));

        /* Move everything flagged as movable */
        BRD_ERR(rm_move_all(pt_boot, pt_boot, pt_m4_0, SC_TRUE,
            SC_TRUE));

        /* Allow all to access the SEMA42 */
        BRD_ERR(rm_set_peripheral_permissions(pt_m4_0,
            SC_R_M4_0_SEMA42, SC_RM_PT_ALL, SC_RM_PERM_FULL));

        /* Move M4 0 TCM */
        BRD_ERR(rm_find_memreg(pt_boot, &mr_m4_0, 0x034FE0000ULL,
            0x034FE0000ULL));
        BRD_ERR(rm_assign_memreg(pt_boot, pt_m4_0, mr_m4_0));

        /* Reserve DDR for M4_0 */
        BRD_ERR(rm_memreg_frag(pt_boot, &mr_m4_0,
            0x088000000ULL, 0x08FFFFFFFULL));
        BRD_ERR(rm_assign_memreg(pt_boot, pt_m4_0, mr_m4_0));

        /* Create shared memory space */
        BRD_ERR(rm_memreg_frag(pt_boot, &mr_m4_0,
            0x090000000ULL, 0x0903FFFFFULL));
        BRD_ERR(rm_assign_memreg(pt_boot, pt_m4_0, mr_m4_0));
        BRD_ERR(rm_set_memreg_permissions(SC_PT, mr_m4_0, pt_boot,
            SC_RM_PERM_FULL));

        /* Reserve FlexSPI for M4_0 */
        BRD_ERR(rm_memreg_frag(pt_boot, &mr_m4_0, 0x08081000ULL,
            0x08180FFFULL));
        BRD_ERR(rm_assign_memreg(pt_boot, pt_m4_0, mr_m4_0));

        /* Move partition to be owned by SC */
        BRD_ERR(rm_set_parent(pt_boot, pt_m4_0, SC_PT));

        /* Move boot to be owned by M4 0 */
        if (no_ap != SC_FALSE)
        {
            BRD_ERR(rm_set_parent(SC_PT, pt_boot, pt_m4_0));
        }

Max

Hi Max,

Thank you for this resource allocation list, it is very helpful.

Can you also share the Toradex DDR configuration file to support the RAM part on the SoM? Thanks!

Hi Brandon

Actually I can’t.

Our legal departments view on the licensing situation is that we are not allowed to give out any source in regards to the SCFW. Sorry about that. Also our direct inquiries towards NXP gave at best an ambiguous answer.

Max