SW reset via SRC_A7RCR0

Hi,
we want to SW reset the A7 cores, so the M4 does not get interrupted by the resetting A7’s.
According to the Reference Manual (IMX7DRM) M4 reset is triggered by COLD and POR. So the last hope for our usecase is for the SW reset not to trigger the M4 reset.

We tried to archieve this by setting the

A7_CORE_RESET0 and
A7_CORE_RESET1
bits of the SRC_A7RCR0 Register to 1.

Edit: The following described Problem was bypassed (see Comment)

This is where we are stuck. According to RM p. 1060 the address of the SRC_A7RCR0 Register is

3039_0004h and it should be set to 00 00 0A 00 after reset.

However reading from it in u-boot via

Colibri iMX7 # i2c md 33 0x30390004 4

returns 30390004: 00 00 00 00

Also writing via

Colibri iMX7 # i2c mw 33 30390004 30000A00 4

does nothing and reading still returns 00 00 00 00

Any ideas about whats going wrong and what else we could try to SW reset the A7’s w/o interrupting the M4?

We bypassed using Colibri iMX7 # i2c by adding “imx-test” with OE to our image to enabled the use of:
root@colibri-imx7-emmc:~# /unit_tests/memtool SRC.A7RCR0 to read and
root@colibri-imx7-emmc:~# /unit_tests/memtool SRC.A7RCR0=0x000A0010 to write
on the A7RCR0 register.
However executing the mentioned write command,
which sets A7_CORE_RESET1 and A7_CORE_RESET0 to 1,
presumably puts both cores into reset state but doesn’t seem to initiate the boot sequence.

I’ll have a closer look at the boot sequence now

The SRC (System Reset Controller) is part of the SoC, there is no need to use the i2c command. The i2c command communicates through the I2C bus to a external device…

md.l 0x30390004 1 should read a single 4-byte value

Note that using this register will really only reset the CPU core. From what I can tell it will not go through the boot ROM and perform a proper boot. Unfortunately the RM is not very clear how to run the core then, but I assume you have to load something in memory beforehand and store the entry point in SRC_GPR1. Also note that this only resets the CPU. All the peripherals are in a random state. Some drivers might have issue to cope with this situation. I am not aware that we tried such a A7 reset only at Toradex, so this goes a bit in uncharted waters…

Not sure what you are trying to archive, but in case you want to reboot Linux into a new kernel you might also consider kexec. It allows to start a new Linux kernel without rebooting/resetting the CPU.

Thanks for your answer!

Our usecase would be to have a safety critical task on the M4 and a non safety critical task on the A7 to reduce certification effort to the baremetal/freertos Code on the M4.

A desired feature of this system would be to reset the A7’s (e.g. on Kernel panic) while keeping the M4 uninterrupted.

Using the watchdogs on the SoC is not an option, because from our understanding the WD’s can only assert PoR/COLD reset which also resets the M4.

So the only option left would be a SW (or warm? not to sure about the terminology) reset.

Is there a way to perform a proper boot through boot ROM?

HI @tik

A desired feature of this system would be to reset the A7’s (e.g. on Kernel panic) while keeping the M4 uninterrupted.

For this you can boot-up a new kernel using second kernel which will be a much easier task than resetting the A7 Core.

So the only option left would be a SW (or warm? not to sure about the terminology) reset.

If you do a soft reset, then you will go through U-Boot and whole boot process which will also reset the M4-core.

Is there a way to perform a proper boot through boot ROM?

This is the regular reset or reboot process.

Best regards,
Jaski