we want to SW reset the A7 cores, so the M4 does not get interrupted by the resetting A7’s.
According to the Reference Manual (IMX7DRM) M4 reset is triggered by COLD and POR. So the last hope for our usecase is for the SW reset not to trigger the M4 reset.
We tried to archieve this by setting the
bits of the SRC_A7RCR0 Register to 1.
Edit: The following described Problem was bypassed (see Comment)
This is where we are stuck. According to RM p. 1060 the address of the SRC_A7RCR0 Register is
3039_0004h and it should be set to
00 00 0A 00 after reset.
However reading from it in u-boot via
Colibri iMX7 # i2c md 33 0x30390004 4
30390004: 00 00 00 00
Also writing via
Colibri iMX7 # i2c mw 33 30390004 30000A00 4
does nothing and reading still returns
00 00 00 00
Any ideas about whats going wrong and what else we could try to SW reset the A7’s w/o interrupting the M4?