Spi-tegra114.0: Error setting SPI clock rate: -22

Hi there,

For reproducability, I tested with the original 2.7 BSP the apalis-tk1 modules do ship with and it’s the same issue: The error in the title shows up in the system messages, the clock rate cannot be changed. So either I there is something wrong with the spidev-driver and everybody should have that problem, but nobody reported (sounds unlikely), or I am missing something (but what? What except for a modprobe spidev could be needed to run the test?).

Original question, for reference:

I added an SPI1 device to my dts:

spi@7000d400 {
  compatible = "nvidia,tegra114-spi";
  #address-cells = <0x1>;
  #size-cells = <0x0>;
  status = "okay";
  spi-max-frequency = <1000000>;

  spidev0 { 
    compatible = "spidev";
    reg = <0>;
    spi-max-frequency = <1000000>;

The new device shows up, but while running the test

Documentation/spi/spidev_test -D /dev/spidev0.0

does a transfer, the dmesg shows two messages of

spi-tegra114 spi-tegra114.0: Error setting SPI clock rate: -22

and the actual clock speed is neither 500 kHz (default of spidev_test) nor 1 MHz, but something like 25 MHz which is to fast for my setting, but I can’t slow it down.

Search engines don’t know this error message.

Thank you for any hint!

What exact hardware and software versions of things are you talking about?

It’s a custom baseboard and a custom BSP, but I can reproduce it with an out-of-the-box Angstrom system as well. see updated question

In default configuration minimum SPI clock on TK1 is 408MHz divided by 128.5 which is ~3.175MHz .

To use lower frequencies you’ll need to change parent clock for this spi peripheral from pll_d ro clk_m. Something like this should work:

diff --git a/arch/arm/mach-tegra/board-apalis-tk1.c b/arch/arm/mach-tegra/board-apalis-tk1.c
index 82e0cfd..d88ccb9 100644
--- a/arch/arm/mach-tegra/board-apalis-tk1.c
+++ b/arch/arm/mach-tegra/board-apalis-tk1.c
@@ -126,7 +126,7 @@ static __initdata struct tegra_clk_init_table apalis_tk1_clk_init_table[] = {
 	{ "i2c4",	"pll_p",	3200000,	false},
 	{ "i2c5",	"pll_p",	3200000,	false},
-	{ "sbc1",	"pll_p",	25000000,	false},
+	{ "sbc1",	"clk_m",	12000000,	false},
    { "sbc2",	"pll_p",	25000000,	false},
 	{ "sbc3",	"pll_p",	25000000,	false},
 	{ "sbc4",	"pll_p",	25000000,	false},
 	{ "sbc5",	"pll_p",	25000000,	false},