I detected sporadic data corruption and it was not so simple to take a shoot.
The iMX7 is the master and it generates the SCLK signal, blue trace and the ~DL_CS signal. The slave system sends data, red trace.
Here we see, that the iMX7 sets the ~DL_CS signal high, and continues clocking, the slave system stops sending data, this is the correct behaviour for getting clock pulses during ~DL_CS is high.
The result is a data loss.
The slave system counting down the transmitted bytes and after a packet is done, it sets ~BRDY high. You see that behaviour during the first two (correct) transfers. After the third transfer, ~BRDY stays low, cause the transfer was disturbed and not all bytes were transmitted.
This happens after transferring about 2.5MB, but it is hard to reproduce, sorry.
Any work around?
With best regards