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Verdin iMX8M Plus M7 SPI Configuration
Understanding SPI Resource Allocation
The issue you’re experiencing is related to resource allocation between the Cortex-A53 (Linux) and Cortex-M7 cores. When using SPI on the M7, you need to ensure the SPI interface is properly disabled in Linux and configured for M7 use(1).
Device Tree Configuration Required
To use SPI on the M7 core, you must first disable the corresponding SPI interface in the Linux device tree. Based on the Verdin iMX8M Plus development documentation, you need to modify the device tree to prevent resource conflicts(1).
The device tree configuration requires creating an imx8mp-verdin-rpmsg.dtsi file with proper memory reservations(1):
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2022 Toradex
*/
#include <dt-bindings/clock/imx8mp-clock.h>
// Enable RPMSG support
/ {
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
/* use linux config instead */
/delete-node/ linux,cma;
/* Allocate 16MB DDR RAM memory for cortex M -> check the ram drr linker file for details */
m7_reserved: m7@0x80000000 {
no-map;
reg = <0 0x80000000 0 0x1000000>;
};
/* Allocate resource table from Cortex-M7 -> check copyResourceTable inside rsc_table.c for details */
rsc_table: rsc_table@550ff000 {
reg = <0 0x550ff000 0 0x1000>;
no-map;
};
/* VDEV0_VRING_BASE 0 comes from FreeRTOS rsc_table.c */
vdev0vring0: vdev0vring0@55000000 {
reg = <0 0x55000000 0 0x8000>;
no-map;
};
/* VDEV0_VRING_BASE 1 comes from FreeRTOS rsc_table.c */
vdev0vring1: vdev0vring1@55008000 {
reg = <0 0x55008000 0 0x8000>;
no-map;
};
/* Buffers to use with RPMSG */
vdevbuffer: vdevbuffer@55400000 {
compatible = "shared-dma-pool";
reg = <0 0x55400000 0 0x100000>;
no-map;
};
};
imx8mp-cm7 {
compatible = "fsl,imx8mp-cm7";
rsc-da = <0x55000000>;
clocks = <&clk IMX8MP_CLK_M7_DIV>;
mbox-names = "tx", "rx", "rxdb";
mboxes = <&mu 0 1
&mu 1 1
&mu 3 1>;
memory-region = <&vdev0vring0>, <&vdev0vring1>, <&vdevbuffer>, <&rsc_table>, <&m7_reserved>;
status = "okay";
};
};
(1)
Pin Configuration for M7
You’ll need to configure the specific pins for SPI use on the M7. The pin configuration must be done using IOMUXC functions in your M7 firmware, similar to the GPIO interrupt example(2):
// Configure SPI pins using IOMUXC functions
IOMUXC_SetPinMux(IOMUXC_[SPI_PIN]_[FUNCTION], 0U);
IOMUXC_SetPinConfig(IOMUXC_[SPI_PIN]_[FUNCTION],
IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK |
IOMUXC_SW_PAD_CTL_PAD_PE_MASK);
(2)
Verdin SPI Pin Mapping
According to the SPI documentation, the Verdin family provides one SPI interface in the “Always Compatible” category(3):
| SODIMM Pin |
Signal Name |
Description |
| 196 |
SPI_1_CLK |
SPI Serial Clock (SCK) |
| 198 |
SPI_1_MISO |
SPI Master Input, Slave Output |
| 200 |
SPI_1_MOSI |
SPI Master Output, Slave Input |
| 202 |
SPI_1_CS |
SPI Chip Select |
(3)
Troubleshooting Steps
- Disable SPI in Linux: You need to disable the SPI interface in the Linux device tree to prevent conflicts
- Configure M7 pins: Use the IOMUXC functions to properly configure the pins for SPI functionality
- Check pin mapping: Ensure you’re using the correct SODIMM pins (196, 198, 200, 202) for SPI signals
- Verify M7 firmware: Make sure your M7 firmware is properly loaded and running
The key issue is that both Linux and M7 cannot use the same SPI controller simultaneously. You must explicitly disable it in Linux and configure it for M7 use.
Best regards, Toradex AI Assistant.
