In one of our application the customer requirement is to get the SPI ADC samples within 20uS.
I tried with iMX6 + ECSPI + kernel ( spi_read function ) but we got time approx 110uS , much more than the value we calculated .
Hence can team please help us with :-
Does toradex team have any pointers w.r.t scratch/ test spi controller driver with which the spi-read activity takes less time ?
The SPI controller driver looks like is using imx51 driver for spi core , as there is no driver binding for "ffsl,imx6q-ecspi " . So could you please confirm that the “imx51-ecspi” is proper binded driver code?
There was an test protocol interface of “spidev” in kernel .
Will using this improve the performance ? .
Because in our kernel driver code (probe function ) we are calling simply an spi-read function .
( The idea was to test with the minimal overhead & hence no involvement of application space code for initial round of testing )
I tried to disable the driver & directly access the escpi register’s but the system enters in panic mode when we try to configure the CLOCK register. Idea was to an scratch SPI read without DMA engine
Does Toradex has any similar test code .
In one of our application the customer requirement is to get the SPI ADC samples within 20uS. I tried with iMX6 + ECSPI + kernel ( spi_read function ) but we got time approx 110uS , much more than the value we calculated .
I doubt that reaching latencies in the range of <100μS will be an easy task, if not impossible.
Please also refer to the Real-Time Linux article.
We at Toradex have no experience in removing ‘avoidable’ delay in the SPI stack.
Yes, the iMX 6 uses the same driver / driver variant as the i.MX 51 for eSPI.
spidev is an interface through the dev filesytem to access the SPI devices from userspace. (/dev/spidevX.Y nodes). Using SPI from userspace will likely add additional asynchronous calls and thus adding additional delay.
I guess your best bet will be to abandon the kernels spi subsystem and write a dedicated driver which combines the handling of the eSPI HW and the external connected SPI device.
The probably fastest AD read is a driver which disables interrupts, starts an AD conversion, busy waits for completion, reads the results and reenables interrupts to get the fastest possible access at the price of a non-portable non-generic software design and worse latency for all other contenders for the CPU.
With DMA channels assigned in the device-tree it will use DMA if the requested transfer does not fit in the hardware FIFO, otherwise it will use PIO mode.
You can disable DMA completely by changing the device-tree.
e.g. overwrite the default dma-names property so that the driver does not have an assigned DMA channel.